NDLI: A DSP-based approach for the implementation of face recognition algorithms

Content Provider	IEEE Xplore Digital Library
Author	Batur, A.U. Flinchbaugh, B.E. Hayes III, M.H.
Copyright Year	2003
Description	Author affiliation: Center for Signal & Image Proc., Georgia Inst. of Technol., Atlanta, GA, USA (Batur, A.U.)
Abstract	Face recognition is an important part of today's emerging biometrics and video surveillance markets. Recent years have witnessed an exploding interest in the development of face recognition algorithms and products. Currently, face recognition systems are usually implemented on general purpose processors. As face recognition algorithms move from research labs to the real world, power consumption and cost become critical issues. This motivates searching for implementations using a digital signal processor (DSP). Our goal is to explore the feasibility of implementing DSP-based face recognition systems. To achieve this goal, we implement a fully automatic face recognition system on Texas Instruments' TMS320C6416 DSP, profile performance, and analyze opportunities for optimization. The results of our experiments demonstrate that a generic C implementation with a modest C level optimization effort results in a face recognition software prototype that has low CPU and memory requirements. Hence, it appears that well-optimized face recognition implementations on DSPs can be an effective choice for embedded face recognition products.
Sponsorship	IEEE Signal Process, Soc
File Size	339311
File Format	PDF
ISBN	0780376633
ISSN	15206149
DOI	10.1109/ICASSP.2003.1202342
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-04-06
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Face recognition Signal processing algorithms Digital signal processing Biometrics Video surveillance Energy consumption Costs Digital signal processors Instruments Performance analysis
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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