NDLI: An efficient implementation of multi-prime RSA on DSP processor

Content Provider	IEEE Xplore Digital Library
Author	Krishnamurthy, A. Yiyan Tang Xu, C. Yuke Wang
Copyright Year	2003
Description	Author affiliation: Dept. of Comput. Sci., Texas Univ. at Dallas, Richardson, TX, USA (Krishnamurthy, A.; Yiyan Tang; Xu, C.; Yuke Wang)
Abstract	The Rivest, Shamir and Adleman (1978) RSA algorithmis a popular cryptography algorithm widely used in signing and encrypting operations for security systems. Generally, the software implementations of the RSA algorithm are based on 2-prime RSA. The multi-prime RSA has been proposed to speed up RSA implementations. Both 2-prime and multi-prime implementations require squaring reduction and multiplication reduction of multi-precision integers. The Montgomery (1985) reduction algorithm is the most efficient for the squaring and multiplication reductions. We present a new method to implement the Montgomery squaring reduction, which speeds up squaring reduction by 10-15% for various key sizes. Furthermore, a multi-prime 1024-bit RSA signing operation is implemented on the TI TMS320C6201 DSP processor with the new reduction method. As a result, the signing operation can be finished within 6 ms, which is about twice faster than the RSA implementation of Itoh, Takenaka, Torii, Temma and Kurihara (see Proc. of CHES'99, p.61-71, 1999) on the same DSP platform.
Sponsorship	IEEE Signal Process, Soc
File Size	278532
File Format	PDF
ISBN	0780376633
ISSN	15206149
DOI	10.1109/ICASSP.2003.1202387
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-04-06
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Public key cryptography Cathode ray tubes Authentication Computer science Computer security Software systems Software algorithms Telecommunication traffic Postal services
Content Type	Text
Resource Type	Article

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