NDLI: Novel 4 GHz Interleaved SRAM Cells With Asymmetrical Precharge in 45 nm PDSOI Technology

Content Provider	IEEE Xplore Digital Library
Author	Joshi, R.V. Kanj, R. Saroop, S.
Copyright Year	1988
Abstract	Novel 9T/8T SRAM cell designs are demonstrated using a fully functional 75-kb L1-cache compatible interleaved hardware based design in 45 nm SOI. An integrated read stack, together with an asymmetrical precharge topology, leads to significant improvement in performance and stability. The proposed cells' yield outperforms that of register file like cells as well as other literature cells. The usage of a larger number of cells on bitlines through statistical simulations indicates that the new cells improve the array efficiency for domino based designs. The extension of the work to 32 nm technology shows the scalability of these cells with lower operating voltage, compared with conventional 6T/8T cells. Hardware based key features include improved read performance/stability, half select stability, and the ability to operate with single read and write wordline over register file like 8T cell. The measured access time improvement is shown to be more than 15% and a Vcsmin reduction of 170 mV is demonstrated at Vdd = 1 V.
Sponsorship	IEEE Electron Devices Society IEEE Components, Packaging, and Manufacturing Technology Society IEEE Reliability Society IEEE Solid-State Circuits Society
Starting Page	278
Ending Page	286
Page Count	9
File Size	14344931
File Format	PDF
ISSN	08946507
Volume Number	27
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit stability Registers Stability criteria SRAM cells Performance evaluation Noise stability SRAM half-select column-decoupled low power 8T differential/domino read
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Condensed Matter Physics Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design

Implementation of low power sram by using 8t decoupled logic.

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique

Decoupled logic based design for implementation low power memories by 8t.

8T Double-Ended Read-Decoupled SRAM

Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

Ground gated 8T SRAM cells with enhanced read and hold data stability

An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving

Novel 4 GHz Interleaved SRAM Cells With Asymmetrical Precharge in 45 nm PDSOI Technology

Similar Documents

A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design

Implementation of low power sram by using 8t decoupled logic.

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique

Decoupled logic based design for implementation low power memories by 8t.

8T Double-Ended Read-Decoupled SRAM

Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

Ground gated 8T SRAM cells with enhanced read and hold data stability

An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving

Novel 4 GHz Interleaved SRAM Cells With Asymmetrical Precharge in 45 nm PDSOI Technology