NDLI: A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design

Content Provider	IEEE Xplore Digital Library
Author	Joshi, R.V. Kanj, R. Ramadurai, V.
Copyright Year	1993
Abstract	We present a novel half-select disturb free transistor SRAM cell. The cell is 6T based and utilizes decoupling logic. It employs gated inverter SRAM cells to decouple the column select read disturb scenario in half-selected columns which is one of the impediments to lowering cell voltage. Furthermore, “false read” before write operation, common to conventional 6T designs due to bit-select and wordline timing mismatch, is eliminated using this design. Two design styles are studied to account for the emerging needs of technology scaling as designs migrate from 90 to 65 nm PD/SOI technology nodes. Namely we focus on a 90 nm PD/SOI sense Amp based and 65 nm PD/SOI domino read based designs. For the sense Amp based design, read disturbs to the fully-selected cell can be further minimized by relying on a read-assist array architecture which enables discharging the bit-line (BL) capacitance to GND during a read operation. This together with the elimination of half-select disturbs enhance the overall array low voltage operability and hence reduce power consumption by 20%-30%. The domino read based SRAM design also exploits the proposed cell to enhance cell stability while reducing the overall power consumption more than 30% by relying on a dynamic dual supply technique in combination of cell design and peripheral circuitry. Because half-selected columns/cells are inherently protected by the proposed scheme, the dynamic supply “High” voltage is only applied to read selected columns/cells, while dynamic supply “Low” is employed in all other situations, thereby reducing the overall design power. A short bitline loading of 16 cells/BL is adopted to achieve high-performance low-power operation and lower bitline capacitance to improve stability. A newly developed fast Monte Carlo based statistical method is used to analyze such a unique cell, and 65 nm design simulations are carried out at 5 GHz. The feasibility of the cell and sensitivity to sense Amp timing has been proved by fabricating a 32 kb array in a 90-nm PD/SOI technology. Hardware experiments and simulation results show improvements of cell Vdd_min over traditional 6T cells by more than 150 mV for 90 nm PD/SOI technology. Also experimental results based on fabricated 65 nm PD/SOI (1.6 kb/site × 80 sites) hardware also asserts half-select disturb elimination and hence the ability to enable significant power savings. The performance and speed are shown to be comparable with the conventional 6T design.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	869
Ending Page	882
Page Count	14
File Size	1812824
File Format	PDF
ISSN	10638210
Volume Number	19
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Partial discharges Voltage Timing Capacitance Energy consumption Hardware Logic Inverters Impedance stability Column-decoupled differential/domino read half-select low power 8T SRAM
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Novel 4 GHz Interleaved SRAM Cells With Asymmetrical Precharge in 45 nm PDSOI Technology

A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array

Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM

A Large $sigma $V$_{rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design

Similar Documents

Novel 4 GHz Interleaved SRAM Cells With Asymmetrical Precharge in 45 nm PDSOI Technology

A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array

Single bit-line 8T SRAM cell with asynchronous dual word-line control for bit-interleaved ultra-low voltage operation

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM

A Large $sigma $V$_{rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design