NDLI: Crystalline ZrTiO<formula formulatype=inline><tex Notation=TeX>$_{bf 4}$</tex></formula>-Gated Ge Metal–Oxide–Semiconductor Devices With Amorphous Yb<formula formulatype=inline><tex Notation=TeX>$_{bf 2}$</tex> </formula>O<formula formulatype=inline><tex Notation=TeX>$_{bf 3}$</tex></formula> as a Passivation Layer

Content Provider	IEEE Xplore Digital Library
Author	Min-Lin Wu Yung-Hsien Wu Chun-Yen Chao Chia-Chun Lin Chao-Yi Wu
Copyright Year	2002
Abstract	An amorphous Yb₂O₃ passivation layer integrated with a crystalline ZrTiO₄ film was explored as the advanced gate stack for Ge MOS devices. The ZrTiO₄/Yb₂O₃ gate stack demonstrates Dit of 2.4 × 10¹¹ cm^-2· eV^-1 and EOT down to 0.76 nm which are, respectively, due to the formation of an interfacial YbGeO_x layer that well passivates the dangling bonds at Ge surface and the adoption of a crystalline ZrTiO₄ film with a κ value of 45.6. The gate stack also shows low leakage current, tight distribution of device parameters, and desirable reliability performance, paving an alternative avenue to develop high-performance Ge MOS devices.
Sponsorship	IEEE Nanotechnology Council
Starting Page	1018
Ending Page	1021
Page Count	4
File Size	421087
File Format	PDF
ISSN	1536125X
Volume Number	12
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Passivation MOS devices Dielectrics Films Leakage currents Annealing Yb$_2$O$_3$ Crystalline ZrTiO$_4$ EOT Ge passivation high-k interface trap density leakage current reliability
Content Type	Text
Resource Type	Article
Subject	Nanoscience and Nanotechnology Electrical and Electronic Engineering Computer Science Applications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Surface Passivation of Ge MOS Devices by ${rm SmGeO}_{bf{x}}$ With Sub-nm EOT

Integration of Amorphous $hbox{Yb}_{2}hbox{O}_{3}$ and Crystalline $hbox{ZrTiO}_{4}$ as Gate Stack for Aggressively Scaled MOS Devices

Low-Leakage TiO$_{bf 2}$ Nanowire Dielectric MOS Device Using Ag Schottky Gate Contact

Two-State Trap-Assisted Tunneling Current Characteristics in $hbox{Al}_{bf 2}hbox{O}_{bf 3}/hbox{SiO}_{bf 2}/hbox{SiC}$ Structures With Ultrathin Dielectrics

High-Performance Ge MOS Capacitors by $hbox{O}_{2}$ Plasma Passivation and $hbox{O}_{2}$ Ambient Annealing

An Ultralow EOT Ge MOS Device With Tetragonal HfO₂ and High Quality Hf_xGe_yO Interfacial Layer

Very low EOT and high oxidation state interfacial layer in Ge MOS devices

Interface-Engineered High-Mobility High-$k$ /Ge pMOSFETs With 1-nm Equivalent Oxide Thickness

Achieving high-performance Ge MOS devices using high-к gate dielectrics Ga2O3(Gd2O3) of sub-nm EOT

Crystalline ZrTiO$_{bf 4}$-Gated Ge Metal–Oxide–Semiconductor Devices With Amorphous Yb$_{bf 2}$ O$_{bf 3}$ as a Passivation Layer

Similar Documents

Surface Passivation of Ge MOS Devices by ${rm SmGeO}_{bf{x}}$ With Sub-nm EOT

Integration of Amorphous $hbox{Yb}_{2}hbox{O}_{3}$ and Crystalline $hbox{ZrTiO}_{4}$ as Gate Stack for Aggressively Scaled MOS Devices

Low-Leakage TiO$_{bf 2}$ Nanowire Dielectric MOS Device Using Ag Schottky Gate Contact

Two-State Trap-Assisted Tunneling Current Characteristics in $hbox{Al}_{bf 2}hbox{O}_{bf 3}/hbox{SiO}_{bf 2}/hbox{SiC}$ Structures With Ultrathin Dielectrics

High-Performance Ge MOS Capacitors by $hbox{O}_{2}$ Plasma Passivation and $hbox{O}_{2}$ Ambient Annealing

An Ultralow EOT Ge MOS Device With Tetragonal HfO2 and High Quality HfxGeyO Interfacial Layer

Very low EOT and high oxidation state interfacial layer in Ge MOS devices

Interface-Engineered High-Mobility High-$k$ /Ge pMOSFETs With 1-nm Equivalent Oxide Thickness

Achieving high-performance Ge MOS devices using high-к gate dielectrics Ga2O3(Gd2O3) of sub-nm EOT

Crystalline ZrTiO$_{bf 4}$-Gated Ge Metal–Oxide–Semiconductor Devices With Amorphous Yb$_{bf 2}$ O$_{bf 3}$ as a Passivation Layer

An Ultralow EOT Ge MOS Device With Tetragonal HfO₂ and High Quality Hf_xGe_yO Interfacial Layer