NDLI: Comparative Study of Silicon-on-Nothing and III–V-on-Nothing Architecture for High Speed and Low Power Analog and RF/Digital Applications

Content Provider	IEEE Xplore Digital Library
Author	Kumari, V. Saxena, M. Gupta, R.S. Gupta, M.
Copyright Year	2002
Abstract	This paper investigates the impact of channel material engineering on the performance of silicon-on-nothing (SON) architecture for 32-nm technology node. The analog performance of SON architecture in terms of drive current I_ds, transconductance (g_m), early voltage V_ea, trans-conductance generation efficiency g_m/I_ds, and output resistance R_out with different channel material, i.e., Si, SiGe, Ge, GaAs, and InP has been investigated by using ATLAS 3D device simulation. The impact of temperature variation on the analog performance of the device has also been studied. Due to high mobility channel material (i.e., for III-V-based MOSFET), device shows excellent performance for microwave application because of its high current gain (h21), unilateral power gain, and maximum available power gain G_ma. Furthermore, the impact of high mobility channel material on the digital performance of the device has also been investigated by monitoring the CMOS inverter characteristics, i.e., voltage transfer characteristics and noise margin.
Sponsorship	IEEE Nanotechnology Council
Starting Page	978
Ending Page	984
Page Count	7
File Size	1592645
File Format	PDF
ISSN	1536125X
Volume Number	12
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Gallium arsenide Indium phosphide Logic gates Silicon germanium MOSFET temperature Analog performance ATLAS inverter materials RF performance
Content Type	Text
Resource Type	Article
Subject	Nanoscience and Nanotechnology Electrical and Electronic Engineering Computer Science Applications

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Ultrathin InAs-channel MOSFETs on Si substrates

Record performance InGaAs homo-junction TFET with superior SS reliability over MOSFET

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Performance Trends of Si-Based RF Transistors

High-power, high-speed for RF photonics applications

Ultra-thin-body self-aligned InGaAs MOSFETs on insulator (III-V-O-I) by a tight-pitch process

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III–V field effect transistors for future ultra-low power applications

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Comparative Study of Silicon-on-Nothing and III–V-on-Nothing Architecture for High Speed and Low Power Analog and RF/Digital Applications

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