NDLI: Behavior Analysis of an LDD Poly-Si TFT Using 2-D Device Simulation

Content Provider	IEEE Xplore Digital Library
Author	Kimura, M.
Copyright Year	1963
Abstract	We have analyzed the device behavior of a poly-Si thin-film transistor (TFT) with a lightly doped drain (LDD) structure using 2-D device simulation. It is found that the reason that the on current does not fall very much is that the electron channel oozes from the channel region to the LDD region and the electric current paths spread to the entire LDD region. On the other hand, the reason that the off current is effectively reduced is undoubtedly that the electric field at the interface between the channel and LDD regions is weakened. However, it should be noted that the depletion region is formed at the drain edge owing to the “pseudo” space-charge region in the channel region, where the carrier density is much lower than in the other channel region, although the net space-charge does not exist.
Sponsorship	IEEE Electron Devices Society
Starting Page	705
Ending Page	709
Page Count	5
File Size	690200
File Format	PDF
ISSN	00189383
Volume Number	59
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thin film transistors Charge carrier density Analytical models Logic gates Educational institutions Awards activities two-dimensional (2-D) device simulation Lightly doped drain (LDD) poly-Si pseudo space-charge region thin-film transistor (TFT)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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