NDLI: Effects of Channel Width and Nitride Passivation Layer on Electrical Characteristics of Polysilicon Thin-Film Transistors

Content Provider	IEEE Xplore Digital Library
Author	Chia-Chun Liao Min-Chen Lin Tsung-Yu Chiang Tien-Sheng Chao
Copyright Year	1963
Abstract	SiN passivation layers were found to yield better performance, suppress the kink effect, and improve the gate leakage current and gate-induced drain leakage (GIDL) of polysilicon thin-film transistors (TFTs). The SiN passivation layers deposited under different deposition conditions possess different characteristics due to their varying passivation effect. A physical mechanism is proposed to explain the double-hump phenomenon induced by incomplete trap passivation. Based on the analysis of width dependence, the better performance of the samples with SiN passivation layers was attributed not only to radical passivation of the defect states but also to radical passivation of preexisting defects in the gate oxide. Furthermore, using SiN passivation layers improves immunity to positive gate bias stress, negative gate bias stress, and hot-carrier stressing. Moreover, the manufacturing processes are simple (without the long processing time plasma treatment requires) and compatible with TFT processes.
Sponsorship	IEEE Electron Devices Society
Starting Page	3812
Ending Page	3819
Page Count	8
File Size	1069872
File Format	PDF
ISSN	00189383
Volume Number	58
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Passivation Silicon compounds Logic gates Thin film transistors Threshold voltage Plasmas Nitrogen radical Gate-induced drain leakage (GIDL) grain boundary intragrain kink effect
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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