NDLI: A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication

Content Provider	IEEE Xplore Digital Library
Author	Hou-Yu Chen Chun-Chi Chen Fu-Kuo Hsueh Jan-Tsai Liu Shyi-Long Shy Cheng-San Wu Chao-Hsin Chien Chenming Hu Chien-Chao Huang Fu-Liang Yang
Copyright Year	1963
Abstract	For more than 45 years, photon- and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection lithography (NInL) technique that employs electron-beam-assisted deposition to form pattern-transfer hard mask in a direct-write deposit approach. By scanning the 4.6-nm-diameter electron beam while injecting a suitable organometallic precursor gas around the location of e-beam and just above the substrate, we form a high-density (pitch: 40 nm) high-uniformity (3-sigma linewidth roughness: 2 nm) hard mask for subsequent etching without using proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. The NInL approach simplifies the hard-mask creation or even metal or dielectric pattern creation process modules from five or tens of steps to only a single step. Therefore, it saves both photomask making and wafer processing costs. In addition, room-temperature NInL deposition of conductor/dielectric materials enables the fabrication of small versatile devices and circuits. For demonstration, we fabricated a functional 16-nm six-transistor static random access memory (SRAM) cell (area: occupying only 0.039 μm²), 43% the size of the smallest previously reported SRAM cell, using the FinFET structure and a dynamic V_dd regulator approach. The NInL technique offers a new way of exploring low-volume high-value 16-nm complementary metal-oxide-semiconductor (CMOS) devices and circuit designs with minimal additional investment and obtains early access to extreme CMOS scaling.
Sponsorship	IEEE Electron Devices Society
Starting Page	3678
Ending Page	3686
Page Count	9
File Size	1089618
File Format	PDF
ISSN	00189383
Volume Number	58
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Lithography Random access memory Resists Fabrication Surface treatment Logic gates static random access memory (SRAM) Direct-write electron beam (e-beam) FinFET nanoinjection lithography (NInL)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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