NDLI: Notice of Violation of IEEE Publication Principles<BR>Redundant Residue Number Systems Based Radiation Hardening for Datapath

Content Provider	IEEE Xplore Digital Library
Author	Lei Li Jianhao Hu
Copyright Year	1963
Abstract	We propose an effective scheme based on redundant residue number systems (RRNS) for radiation hardening of datapath in this paper. The proposed hardening scheme employs redundant residues to mitigate soft errors. We use the properties of RRNS, such as independence, parallel and error correction, to establish the radiation hardening architecture for datapath in radiation environments. In the architecture, all of the residues can be processed independently, and most of soft errors in datapath can be corrected with the redundant relationship of the residues at correction module, which is allocated at the end of the architecture. There is not any additional processing in the architecture but correction operation and binary to residue translation. Thus, the proposed scheme has high efficiency when the processing steps of datapath are large. In order to provide protection for the key module in the proposed scheme, correction module, some traditional protection methods, including Guard-gate register triple modular redundancy (G-RTMR), pipeline-level TMR, and module-level TMR, are used to construct the hybrid protection schemes. In the case studies, we find that the RRNS based scheme and the hybrid schemes can reduce soft error rate from 10^-12 to 10^-17, 10^-18, 10^-25, and 10^-25, respectively, only with 45.6-46.1% area overheads and negligible latency overheads, when the pipeline stages of datapath are 10⁴ and the moduli set with correction capability of one residue is adopted. The case studies also show that the proposed schemes can achieve less area and latency overheads than that of datapath without radiation hardening, because RRNS can reduce the complexity of operations in datapath.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	2332
Ending Page	2343
Page Count	12
File Size	623759
File Format	PDF
ISSN	00189499
Volume Number	57
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radiation hardening Protection Logic Error correction Delay P-n junctions Latches Registers Digital signal processing CMOS technology SEUs RHBD RRNS SETs
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Notice of Violation of IEEE Publication Principles
Joint Redundant Residue Number Systems and Module Isolation for Mitigating Single Event Multiple Bit Upsets in Datapath

Sense amplifier based RADHARD flip flop design

A Radiation Hardened by Design Register File With Lightweight Error Detection and Correction

A Dual Mode Redundant Approach for Microprocessor Soft Error Hardness

A New Error Correction Circuit for Delay Locked Loops

Edge triggered pulse latch design with delayed latching edge for radiation hardened application

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 $mu$ m

Single-Event Tolerant Latch Using Cascode-Voltage Switch Logic Gates

SEU and SET of 65 Bulk CMOS Flip-flops and Their Implications for RHBD

Notice of Violation of IEEE Publication Principles
Redundant Residue Number Systems Based Radiation Hardening for Datapath

Similar Documents

Notice of Violation of IEEE Publication PrinciplesJoint Redundant Residue Number Systems and Module Isolation for Mitigating Single Event Multiple Bit Upsets in Datapath

Sense amplifier based RADHARD flip flop design

A Radiation Hardened by Design Register File With Lightweight Error Detection and Correction

A Dual Mode Redundant Approach for Microprocessor Soft Error Hardness

A New Error Correction Circuit for Delay Locked Loops

Edge triggered pulse latch design with delayed latching edge for radiation hardened application

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 $mu$ m

Single-Event Tolerant Latch Using Cascode-Voltage Switch Logic Gates

SEU and SET of 65 Bulk CMOS Flip-flops and Their Implications for RHBD

Notice of Violation of IEEE Publication PrinciplesRedundant Residue Number Systems Based Radiation Hardening for Datapath

Notice of Violation of IEEE Publication Principles
Joint Redundant Residue Number Systems and Module Isolation for Mitigating Single Event Multiple Bit Upsets in Datapath

Notice of Violation of IEEE Publication Principles
Redundant Residue Number Systems Based Radiation Hardening for Datapath