NDLI: FinFET SRAM Optimization With Fin Thickness and Surface Orientation

Content Provider	IEEE Xplore Digital Library
Author	Mingu Kang Song, S.C. Woo, S.H. Park, H.K. Abu-Rahma, M.H. Ge, L. Han, B.M. Wang, J. Yeap, G. Jung, S.O.
Copyright Year	1963
Abstract	In this paper, the design space, including fin thickness (T_fin), fin height (H_fin), fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints. The simulation results, which consider the variations of both T_fin and threshold voltage (V_th), show that most FinFET SRAM configurations achieve a superior read/write noise margin when compared with planar SRAMs. However, when two fins are used as pass gate transistors (PG) in FinFET SRAMs, enormous array dynamic energy is required due to the increased effective gate and drain capacitance. On the other hand, a FinFET SRAM with a one-fin PG in the (110) plane shows a smaller write noise margin than the planar SRAM. Thus, the one-fin PG in the (100) plane is suitable for FinFET SRAM design. The one-fin PG FinFET SRAM with T_fin = 10 nm and H_fin = 40 nm in the (100) plane achieves a three times larger noise margin when compared with the planar SRAM and consumes a 17% smaller bit-line toggling array energy at a cost of a 22% larger word-line toggling energy. It also achieves a 2.3 times smaller read delay and a 30% smaller write delay when compared with the planar SRAM.
Sponsorship	IEEE Electron Devices Society
Starting Page	2785
Ending Page	2793
Page Count	9
File Size	1143115
File Format	PDF
ISSN	00189383
Volume Number	57
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Random access memory SRAM chips Leakage current write stability Cell current FinFET leakage current read stability SRAM surface orientation
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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