NDLI: High-Speed and High-Reliability InP-Based HBTs With a Novel Emitter

Content Provider	IEEE Xplore Digital Library
Author	Kashio, N. Kurishima, K. Fukai, Y.K. Ida, M. Yamahata, S.
Copyright Year	1963
Abstract	This paper describes InP HBTs with a novel emitter simply consisting of a degenerately doped n⁺-InGaAs layer and an undoped InP thin layer. An n⁺-InP layer is not necessary because the quasi-Femi level in the n⁺-InGaAs layer is high enough to exceed the conduction band discontinuity between the n⁺ -InGaAs layer and the undoped InP layer. In the proposed structure, a thin ( ~ 10 nm) ledge structure can easily be fabricated by etching the n⁺-InGaAs layer. The fabricated HBTs with a 15-nm-thick ledge structure provide a high collector current density of over 6 mA/¿m² . There is almost no degradation of current gain, although the emitter width is reduced to as small as 0.5 ¿m. The HBTs also exhibit an ft of 324 GHz at a collector current density of 5.5 mA/¿m², which is comparable with that of HBTs with a conventional emitter consisting of an n⁺ -InGaAs layer, an n⁺-InP layer, and an n-InP layer. From the results of accelerated life tests, the activation energy of the degradation in HBTs is estimated to be around 1.8 eV, and the extrapolated mean time to failure is estimated to be over 10⁸ h at a junction temperature of 125°C.
Sponsorship	IEEE Electron Devices Society
Starting Page	373
Ending Page	379
Page Count	7
File Size	364591
File Format	PDF
ISSN	00189383
Volume Number	57
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Heterojunction bipolar transistors Indium phosphide Indium gallium arsenide Junctions Degradation Stress Reliability reliability Current gain InP heterojunction bipolar transistor (HBT) ledge passivation
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reliability study on InP/InGaAs emitter-base junction for high-speed and low-power InP HBT

Over 450-GHz f_t and f_max InP/InGaAs DHBTs With a Passivation Ledge Fabricated by Utilizing SiN/SiO₂ Sidewall Spacers

Extrinsic Base Surface Passivation in Terahertz GaAsSb/InP DHBTs Using InGaAsP Ledge Structures

High-performance self-aligned InP/InGaAs DHBTs with a passivation ledge utilizing a thin etching stop layer

High-current-gain InP DHBTs with a passivation ledge demonstrating ft and fmax of over 440 GHz

Reliability of InGaAs/InP HBTs with InP passivation structure

0.25 μm emitter InP/InAlGaAs/GaAsSb double heterojunction bipolar transistor with passivation ledge exhibiting a current gain of over 100

Analytical modelling of base transit time and gain of InP/InGaAs HBTs including effect of temperature

InAlAs/InP/InGaAs/InP DHBTs with a novel composite-emitter design

High-Speed and High-Reliability InP-Based HBTs With a Novel Emitter

Similar Documents

Reliability study on InP/InGaAs emitter-base junction for high-speed and low-power InP HBT

Over 450-GHz ft and fmax InP/InGaAs DHBTs With a Passivation Ledge Fabricated by Utilizing SiN/SiO2 Sidewall Spacers

Extrinsic Base Surface Passivation in Terahertz GaAsSb/InP DHBTs Using InGaAsP Ledge Structures

High-performance self-aligned InP/InGaAs DHBTs with a passivation ledge utilizing a thin etching stop layer

High-current-gain InP DHBTs with a passivation ledge demonstrating ft and fmax of over 440 GHz

Reliability of InGaAs/InP HBTs with InP passivation structure

0.25 μm emitter InP/InAlGaAs/GaAsSb double heterojunction bipolar transistor with passivation ledge exhibiting a current gain of over 100

Analytical modelling of base transit time and gain of InP/InGaAs HBTs including effect of temperature

InAlAs/InP/InGaAs/InP DHBTs with a novel composite-emitter design

High-Speed and High-Reliability InP-Based HBTs With a Novel Emitter

Over 450-GHz f_t and f_max InP/InGaAs DHBTs With a Passivation Ledge Fabricated by Utilizing SiN/SiO₂ Sidewall Spacers