NDLI: Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

Content Provider	IEEE Xplore Digital Library
Author	Shrivastava, M. Baghini, M.S. Gossner, H. Rao, V.R.
Copyright Year	1963
Abstract	In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate-drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.
Sponsorship	IEEE Electron Devices Society
Starting Page	448
Ending Page	457
Page Count	10
File Size	1190460
File Format	PDF
ISSN	00189383
Volume Number	57
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Performance evaluation CMOS integrated circuits Resistance Junctions CMOS technology Implants reliability Drain-extended MOS (DeMOS) hot carrier input/output lightly doped drain MOS (LDDMOS) mixed signal reduced surface field (RESURF)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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Part II: A Novel Scheme to Optimize the Mixed-Signal Performance and Hot-carrier Reliability of Drain-Extended MOS Devices

Breakdown Voltage Model and Electrical Characteristics of CMOS Compatible RESURF STI Drain Extended MOS Transistors

Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs

Anomalous Reduction of Hot-Carrier-Induced On-Resistance Degradation in n-Type DEMOS Transistors

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

Convergence of Hot-Carrier-Induced Saturation Region Drain Current and On-Resistance Degradation in Drain Extended MOS Transistors

Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device

Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain-Extended pMOS Device

An Accurate and Robust Compact Model for High-Voltage MOS IC Simulation

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

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