NDLI: Architecture of a Slow-Control ASIC for Future High-Energy Physics Experiments at SLHC

Content Provider	IEEE Xplore Digital Library
Author	Gabrielli, A. De Robertis, G. Fiore, D. Loddo, F. Ranieri, A.
Copyright Year	1963
Abstract	This work is aimed at defining the architecture of a new digital ASIC, namely slow control logic (SCL), which will be designed and fabricated in a commercial 130 nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics proposed for future high-energy physics experiments at the super-Large Hadron Collider (SLHC), CERN, Geneva. The GBT link provides a transparent transport layer between the SCL and control electronics in the counting room. It will be provided with rad-hard redundant logic for critical circuits. The project follows a set of designs that were recently developed via a 250 nm CMOS technology for LHC experiments. Since this 250 nm specific technology used to design ASICs for the LHC will no longer be available as it was in the past, requesting an update technology for future experiments must be satisfied in any case. A test chip that implements three different redundant methodologies against single event effects is also described.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	1163
Ending Page	1167
Page Count	5
File Size	421623
File Format	PDF
ISSN	00189499
Volume Number	56
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Physics CMOS technology CMOS logic circuits Large Hadron Collider Logic design Data acquisition Optical fiber communication Optical control Monitoring single event effects GBT radiation hardness SCL
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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