NDLI: Metallized ultra-shallow-junction device technology for sub-0.1 /spl mu/m gate MOSFET's

Content Provider	IEEE Xplore Digital Library
Author	Hisamoto, D. Nakamura, K. Saito, M. Kobayashi, N. Kimura, S. Nagai, R. Nishida, T. Takeda, E.
Copyright Year	1963
Abstract	This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 /spl mu/m MOSFET's. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability.<>
Sponsorship	IEEE Electron Devices Society
Starting Page	745
Ending Page	750
Page Count	6
File Size	683782
File Format	PDF
ISSN	00189383
Volume Number	41
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Metallization MOSFET circuits Tungsten Parasitic capacitance Electrodes Contact resistance Impurities Fabrication Silicides Wafer bonding
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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