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Evidence of processing non-idealities in 4h-sic integrated circuits fabricated with two levels of metal interconnect
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Spry, David J. Lukco, Dorothy Neudeck, Philip G. Chang, Carl W. Beheim, Glenn M. Evans, Laura J. Chen, Liangyu |
| Copyright Year | 2015 |
| Description | The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.|||||||||||||||| |
| File Size | 2661041 |
| Page Count | 1 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_20150023024 |
| Archival Resource Key | ark:/13960/t1mh2mq1x |
| Language | English |
| Publisher Date | 2015-10-04 |
| Access Restriction | Open |
| Subject Keyword | Jfet Silicon Carbide Microelectronics Degradation Fabrication Integrated Circuits Wafers Transistor Circuits Dielectrics Carbides Failure Ion Beams Crack Initiation Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Presentation |
