Loading...
Please wait, while we are loading the content...
Similar Documents
Processing and prolonged 500 c testing of 4h-sic jfet integrated circuits with two levels of metal interconnect (Document No: 20150023022)
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Spry, David J. Lukco, Dorothy Neudeck, Philip G. Chang, Carl W. Beheim, Glenn M. Krasowski, Michael J. Prokop, Norman F. Chen, Liangyu |
| Copyright Year | 2015 |
| Description | Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. |
| File Size | 9685409 |
| Page Count | 17 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_20150023022 |
| Archival Resource Key | ark:/13960/t45q9xp7m |
| Language | English |
| Publisher Date | 2015-10-04 |
| Access Restriction | Open |
| Subject Keyword | Silicon Carbide Microelectronics Jfet Integrated Circuits Failure Analysis Life Durability Random Access Memory High Temperature Tests Silicon Carbides Reliability Analysis Circuit Boards Bus Conductors Oscillators Decoders Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Presentation |
