NDLI: The Thermal-Circuit High-Speed Collaboration Layout Design for an Electronic System With Multi-Agent Method

Content Provider	The American Society of Mechanical Engineers (ASME) Digital Collection
Author	Hayashi, Shintaro Iwata, Yoshiharu Satoh, Ryohei Fujimoto, Kozo
Copyright Year	2007
Abstract	Recently, electronics systems have become more complex resulting in a need for system design method that considers multiple physical phenomenons. However, it is difficult at the electronic system design level to reduce the design time and realize high precision. We have developed a collaborative highspeed thermal/circuit design method with a modularized model [1–2]. In this paper, we reconsider the optimization method of this design system. We obtain the local minimum solution for a very high-density device system. However, because the constraints associated with both thermal and electrical design become very strong, we applied an agent-oriented optimization method in defining the boundary conditions between device module and board module to ease the constraints on the thermal layout design. This method is characterized by making the design for device module design intelligent. In a case study, we achieved more than a 20% improvement in the design solution in the Pareto curve. We also reduced the design time by more than 10 times (one weight pattern: about 30sec, Pareto solution set: about 600sec). This enables the designer of electronics system to compare Pareto solution sets within a short time and to evaluate many different layout designs during the rough design phase of a system design.
Sponsorship	Electronic and Photonic Packaging Division
Starting Page	679
Ending Page	685
Page Count	7
File Format	PDF
ISBN	0791842789
DOI	10.1115/IPACK2007-33982
e-ISBN	0791838013
Volume Number	ASME 2007 InterPACK Conference, Volume 2
Conference Proceedings	ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference
Language	English
Publisher Date	2007-07-08
Publisher Place	Vancouver, British Columbia, Canada
Access Restriction	Subscribed
Subject Keyword	Design Electronic systems Circuit design Design methodology Circuits Collaboration Weight (mass) Electronics Boundary-value problems Surface roughness Density Optimization
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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