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| Content Provider | The American Society of Mechanical Engineers (ASME) Digital Collection |
|---|---|
| Author | Cader, T. Tolman, B. Tilton, C. Harris, M. C. |
| Copyright Year | 2003 |
| Abstract | Semiconductor logic burn-in is a process during which potentially large quantities of devices are subjected to elevated temperatures and voltages in order to accelerate latent reliability defects and processing problems to failure prior to customer delivery. During burn-in, there is typically a large variation in the device power levels as well as a product-specific maximum burn-in temperature. Such variations result in a wide device temperature distribution (i.e., device temperature spread), which lowers the median allowable device temperature for the lot. Burn-in time is directly related to the median device temperature, in the sense that the lower the median temperature, the longer the required burn-in time. An optimum thermal management solution is one that is reliable, low-cost, enables a high median device temperature, and maximizes device throughput. Current thermal solutions include forced convection air-cooling, single-phase liquid-cooled heat sinks, and thermoelectric coolers. Some of the solutions employ thermal interface materials, as well as an active thermal control scheme for minimization of device temperature spread. All current solutions also employ an engage mechanism that places the thermal solution in contact with the device under test (DUT). The thermal solution at each DUT is typically gimbaled in an effort to ensure uniform contact pressure between the cooling head and device. The present study deals with the application of direct spray cooling of semiconductor devices undergoing burn-in: this approach negates the need for an actuation mechanism and thermal interface material, is capable of reduced junction temperature spread via active thermal control, and results in reduced across device temperature “gradients”. A spray cooled burn-in slot level prototype was built to accommodate single burn-in boards for bare DUTs as well as small and large lidded DUTs. The solution was investigated primarily for thermal capability and device-to-device junction temperature spread, but results were also obtained for on-DUT thermal “gradients”. For the specific test conditions selected, the heat flux removal capability demonstrated was 146W/cm2 for the bare DUT, 136W/cm2 for the small lidded DUT, and 63W/cm2 for the large lidded DUT. For each DUT investigated, and through the use of active flow control, the device temperature spread between two devices running at a 50% difference in power levels was shown to be less than 1°C. |
| Sponsorship | Electronic and Photonic Packaging Division |
| Starting Page | 65 |
| Ending Page | 71 |
| Page Count | 7 |
| File Format | |
| ISBN | 0791836908 |
| DOI | 10.1115/IPACK2003-35137 |
| e-ISBN | 0791836746 |
| Volume Number | 2003 International Electronic Packaging Technical Conference and Exhibition, Volume 1 |
| Conference Proceedings | ASME 2003 International Electronic Packaging Technical Conference and Exhibition |
| Language | English |
| Publisher Date | 2003-07-06 |
| Publisher Place | Maui, Hawaii, USA |
| Access Restriction | Subscribed |
| Subject Keyword | Semiconductors (materials) Temperature distribution Temperature Forced convection Cooling Semiconductor devices Sprays Pressure Heat flux Flow control Thermal management Reliability Junctions Engineering prototypes Heat sinks Thermoelectric coolers Failure Lumber |
| Content Type | Text |
| Resource Type | Article |
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