NDLI: Lazy cache invalidation for self-modifying codes

Please wait, while we are loading the content...

Wireless innovations for smartphones

Internet-of-energy: combining embedded computing and communication for the smart grid

Side channel attacks and the non volatile memory of the future

From sequential programming to flexible parallel execution

Power agnostic technique for efficient temperature estimation of multicore embedded systems

Siblingrivalry: online autotuning through local competitions

Energy efficient hybrid display and predictive models for embedded and mobile systems

Lazy cache invalidation for self-modifying codes

Architectural synthesis of flow-based microfluidic large-scale integration biochips

DaaC: device-reserved memory as an eviction-based file cache

Analytical approaches for performance evaluation of networks-on-chip

Embedded reconfigurable architectures

Computing without processors

Trends in automotive embedded systems

A cost-effective tag design for memory data authentication in embedded systems

A hybrid just-in-time compiler for android: comparing JIT types and the result of cooperation

Scenario-based design flow for mapping streaming applications onto on-chip many-core systems

Function inlining and loop unrolling for loop acceleration in reconfigurable processors

Energy efficient special instruction support in an embedded processor with compact isa

Static task partitioning for locked caches in multi-core real-time systems

Integrating software caches with scratch pad memory

A standards-based, fully-open software platform for smart embedded systems

Research issues in smart phones, notepads and related services

Static secure page allocation for light-weight dynamic information flow tracking

LLBT: an LLVM-based static binary translator

The RACECAR heuristic for automatic function specialization on multi-core heterogeneous systems

A low-overhead interconnect architecture for virtual reconfigurable fabrics

When less is more (LIMO):controlled parallelism forimproved efficiency

Revisiting level-0 caches in embedded processors

Lazy cache invalidation for self-modifying codes

Content Provider	ACM Digital Library
Author	Mudge, Trevor Dreslinski, Ronald G. Pusdesris, Joseph Gutierrez, Anthony
Abstract	Just-in-time compilation with dynamic code optimization is often used to help improve the performance of applications that utilize high-level languages and virtual run-time environments, such as those found in smartphones. Just-in-time compilation introduces additional overhead into the instruction fetch stage of a processor that is particularly problematic for user applications-instruction cache invalidation due to the use of self-modifying code. This software-assisted cache coherence serializes cache line invalidations, or causes a costly invalidation of the entire instruction cache, and prevents useful instructions from being fetched for the period during which the stale instructions are being invalidated. This overhead is not acceptable for user applications, which are expected to respond quickly. In this work we introduce a new technique that can, using a single instruction, invalidate cache lines in page-sized chunks as opposed to invalidating only a single line at a time. Lazy cache invalidation reduces the amount of time spent stalling due to instruction cache invalidation by removing stale instructions on demand as they are accessed, as opposed to all at once. The key observation behind lazy cache invalidation is that stale instructions do not necessarily need to be removed from the instruction cache; as long as it is guaranteed that attempts to fetch stale instructions will not hit in the instruction cache, the program will behave as the developer had intended.
Starting Page	151
Ending Page	160
Page Count	10
File Format	PDF
ISBN	9781450314244
DOI	10.1145/2380403.2380433
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-10-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Instruction caching Software-assisted coherence Architecture Self-modifying code
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Two-phase write posting on symmetric multiprocessors.

Software-based instruction caching for embedded processors

ASCMS: An Accurate Self-Modifying Code Cache Management Strategy in Binary Translation

POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics

Enhancing cache invalidation in mobile environments

Pacman: program-assisted cache management ⇤.

A new perspective for efficient virtual-cache coherence

Cache invalidation and propagation in distributed caching

A Lazy-Updating Snoop Cache Protocol for Transactional Memory

Lazy cache invalidation for self-modifying codes

Similar Documents

Two-phase write posting on symmetric multiprocessors.

Software-based instruction caching for embedded processors

ASCMS: An Accurate Self-Modifying Code Cache Management Strategy in Binary Translation

POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics

Enhancing cache invalidation in mobile environments

Pacman: program-assisted cache management ⇤.

A new perspective for efficient virtual-cache coherence

Cache invalidation and propagation in distributed caching

A Lazy-Updating Snoop Cache Protocol for Transactional Memory

Lazy cache invalidation for self-modifying codes