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Two-phase write posting on symmetric multiprocessors.
| Content Provider | CiteSeerX |
|---|---|
| Author | Chung, Byung-Kwon Sun, Yongjoon Lee Peir, Jih-Kwon Lai, Konrad |
| Abstract | Cache coherence activities with writeinvalidate protocol in Symmetric Multiprocessors not only incur overhead but may increase cache miss ratios due to unnecessary invalidations. Under software synchronization models, a lazy cache coherence protocol delays write invalidations and permits inconsistent copies of the same cache line existing in different caches. In this paper, we propose a demand-driven two-phase deferred cache coherence model which further delays writes to be observed by other processors until a processor requests the new data after certain synchronization instructions. Data dependence can be maintained by identifying when the new data must be fetched and reconciled. Cycle-by-cycle execution-driven simulation of SPLASH-2 workload shows that the two-phase deferred coherence protocol can out-perform the eager protocol up to 30% for some workload. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Symmetric Multiprocessor Two-phase Write New Data Data Dependence Writeinvalidate Protocol Coherence Protocol Write Invalidation Lazy Cache Coherence Protocol Permit Inconsistent Copy Cache Coherence Activity Splash-2 Workload Demand-driven Two-phase Different Cache Unnecessary Invalidation Cache Miss Ratio Cycle-by-cycle Execution-driven Simulation Cache Line Software Synchronization Model Cache Coherence Model Certain Synchronization Instruction |
| Content Type | Text |
