NDLI: Revisiting level-0 caches in embedded processors

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Revisiting level-0 caches in embedded processors

Content Provider	ACM Digital Library
Author	Zhao, Dali Duong, Nam Kim, Taesu Veidenbaum, Alexander V.
Abstract	Level-0 (L0) caches have been proposed in the past as an inexpensive way to improve performance and reduce energy consumption in resource-constrained embedded processors. This paper proposes new L0 data cache organizations using the assumption that an L0 hit/miss determination can be completed prior to the L1 access. This is a realistic assumption for very small L0 caches that can nevertheless deliver significant miss rate and/or energy reduction. The key issue for such caches is how and when to move data between the L0 and L1 caches. The first new cache, a flow cache, targets a conflict miss reduction in a direct-mapped L1 cache. It offers a simpler hardware design and uses on average 10% less dynamic energy than the victim cache with nearly identical performance. The second new cache, a hit cache, reduces the dynamic energy consumption in a set-associative L1 cache by 30% without impacting performance. A variant of this policy reduces the dynamic energy consumption by up to 50%, with 5% performance degradation.
Starting Page	171
Ending Page	180
Page Count	10
File Format	PDF
ISBN	9781450314244
DOI	10.1145/2380403.2380435
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-10-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Migration policy Conflict misses Level-0 cache Dynamic energy Cache design
Content Type	Text
Resource Type	Article

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