NDLI: Adding a new dimension to physical design

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Going with the flow: bridging the gap between theory and practice in physical design

Thinking outside of the chip

Analog layout synthesis: what's missing?

Adding a new dimension to physical design

Logical and physical restructuring of fan-in trees

Dummy fill optimization for enhanced manufacturability

Skew management of NBTI impacted gated clock trees

Impact of local interconnects on timing and power in a high performance microprocessor

SafeChoice: a novel clustering algorithm for wirelength-driven placement

Physical design of biological systems

Design planning trends and challenges

B-escape: a simultaneous escape routing algorithm based on boundary routing

Design platform for electrical and physical co-design of analog circuits

Physical design implementation for 3D IC: methodology and tools

Ultra-fast interconnect driven cell cloning for minimizing critical path delay

Density gradient minimization with coupling-constrained dummy fill for CMP control

Accurate clock mesh sizing via sequential quadraticprogramming

Interconnect power and delay optimization by dynamic programming in gridded design rules

Droplet-routing-aware module placement for cross-referencing biochips

What makes a design difficult to route

FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction

Automatic generation of hierarchical placement rules for analog integrated circuits

Efficient design practices for thermal management of a TSV based 3D IC system

ITOP: integrating timing optimization within placement

Total sensitivity based dfm optimization of standard library cells

ISPD 2010 high performance clock network synthesis contest: benchmark suite and results

Performance study of VeSFET-based, high-density regular circuits

A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochips

Physical design challenges beyond the 22nm node

Completing high-quality global routes

An analytical placer for mixed-size 3D placement

Physical synthesis of bus matrix for high bandwidth low power on-chip communications

A matching based decomposer for double patterning lithography

A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems

Challenges and opportunities in optimization of automotive electronics

Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles

Adding a new dimension to physical design

Content Provider	ACM Digital Library
Author	Sapatnekar, Sachin S.
Abstract	Three-dimensional (3D) technologies have the potential to provide major benefits to integrated circuit design. An advanced 3D chip consists of multiple tiers of two-dimensional (2D) circuitry, stacked vertically over each other, with very small intertier distances. Such technologies offer numerous benefits over conventional 2D designs. First, by stacking multiple 2D tiers, it is possible to increase the number of transistors within a package: in other words, 3D offers increased integration using an approach that is orthogonal to device scaling. Second, the small intertier distances imply that the histogram of wire length distributions is significantly altered, enabling critical wires to be made very short. Third, 3D offers opportunities for integrating heterogeneous technologies into a single chip, enabling much more versatility in the types of chips we can build. Fundamentally, the shift from 2D to 3D is topological, and holds numerous physical design challenges. In addition, several effects that were critical in 2D are further accentuated in 3D. For example, the increased current required by a 3D stack, as compared to a 2D chip with the same footprint, brings forth twin problems: how do we get the current in (i.e., perform reliable power delivery), and how do we get the heat out (i.e., perform thermal management)? Solutions to problems such as these can come from the architectural level and go down to much finer granularities. This talk overviews prior work in the area, and surveys the challenges and opportunities ahead.
Starting Page	55
Ending Page	55
Page Count	1
File Format	PDF
ISBN	9781605589206
DOI	10.1145/1735023.1735041
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-03-14
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	3d circuits Physical design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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