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| Content Provider | ACM Digital Library |
|---|---|
| Author | Sze, C. N. |
| Abstract | In the talk, the details of ISPD 2010 high performance clock network synthesis contest will be introduced. Compared to first clock network synthesis contest in 2009, the rules have been revised to better reflect the real problems from the industry. Instead of clock latency range upon two simulations with different supply voltage settings, the total clock power (modeled by capacitance) is set to be the major judging criteria. However, a valid clock distribution network solution must have local clock skew under a preset limit. Only local clock skew constraints will be enforced because (1) early mode timing violations are often limited in local regions, and (2) local timing violations often directly lead to congestion problems which are very hard to fix. Moreover, delay variation will be formulated in the contest and simplified Monte Carlo simulation will be used to evaluate valid solutions. More importantly, a new set of benchmarks will be announced and used to decide the winner of the contest. These test-cases are all directly derived from real industrial microprocessor and high-performance ASIC designs and they have over 1000 clock sinks. More than ten academic clock synthesis tools have participated in the contest and the final results will be announced during this talk. |
| Starting Page | 143 |
| Ending Page | 143 |
| Page Count | 1 |
| File Format | |
| ISBN | 9781605589206 |
| DOI | 10.1145/1735023.1735058 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2010-03-14 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Vlsi Clock network synthesis Benchmarks Physical design |
| Content Type | Text |
| Resource Type | Article |
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