NDLI: Proceedings of the 19th international symposium on Physical design (ISPD '10)

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Going with the flow: bridging the gap between theory and practice in physical design

Thinking outside of the chip

Analog layout synthesis: what's missing?

Adding a new dimension to physical design

Logical and physical restructuring of fan-in trees

Dummy fill optimization for enhanced manufacturability

Skew management of NBTI impacted gated clock trees

Impact of local interconnects on timing and power in a high performance microprocessor

SafeChoice: a novel clustering algorithm for wirelength-driven placement

Physical design of biological systems

Design planning trends and challenges

B-escape: a simultaneous escape routing algorithm based on boundary routing

Design platform for electrical and physical co-design of analog circuits

Physical design implementation for 3D IC: methodology and tools

Ultra-fast interconnect driven cell cloning for minimizing critical path delay

Density gradient minimization with coupling-constrained dummy fill for CMP control

Accurate clock mesh sizing via sequential quadraticprogramming

Interconnect power and delay optimization by dynamic programming in gridded design rules

Droplet-routing-aware module placement for cross-referencing biochips

What makes a design difficult to route

FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction

Automatic generation of hierarchical placement rules for analog integrated circuits

Efficient design practices for thermal management of a TSV based 3D IC system

ITOP: integrating timing optimization within placement

Total sensitivity based dfm optimization of standard library cells

ISPD 2010 high performance clock network synthesis contest: benchmark suite and results

Performance study of VeSFET-based, high-density regular circuits

A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochips

Physical design challenges beyond the 22nm node

Completing high-quality global routes

An analytical placer for mixed-size 3D placement

Physical synthesis of bus matrix for high bandwidth low power on-chip communications

A matching based decomposer for double patterning lithography

A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems

Challenges and opportunities in optimization of automotive electronics

Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles

Proceedings of the 19th international symposium on Physical design (ISPD '10)

Content Provider	ACM Digital Library
Editor	Chang, Yao-Wen Saxena, Prashant
Copyright Year	2010
Abstract	On behalf of the organizing committee for the 2010 ACM International Symposium on Physical Design (ISPD), we are delighted to welcome you to San Francisco, California for the symposium, being held from March 14th to March 17th, 2010. Like its eighteen predecessors, the 2010 ISPD provides a premier forum to bring out emerging challenges, present cutting-edge research results, exchange implementation experiences, identify future research directions, and record advances in theoretical and empirical techniques for problems related to the physical design of VLSI and other analogous systems (such as bio-chips). Furthermore, the 2010 ISPD is co-located with the ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), in an effort to further our attempts to collaborate with related events for higher impact on the electronic design automation (EDA) community. This year we received more than 70 submissions from all over the world. After a rigorous blind review process that culminated in a full-day face-to-face meeting of the entire technical program committee, only 22 regular papers were selected for inclusion. In addition, the program is further enriched with one keynote speech and thirteen invited talks presented by distinguished researchers in both industry and academia. The scope of these talks covers all aspects of physical design---from front-end logic and physical synthesis to back-end yield optimization and design for manufacturing, from VLSI circuitry to biological systems, from digital design to analog methodologies, from on-chip optimization to beyond-die design, and from 2D synthesis to 3D integration. As a highlight of ISPD's focus on emerging applications in non-traditional domains, we are very fortunate in having Dr. Louis Scheffer from the Howard Hughes Medical Institute at Janelia Farm to address the physical design of biological systems. Continuing the forwardlooking theme, this keynote talk will be followed by an invited session on modern physical design challenges featuring several distinguished researchers from leading EDA vendors and a research institution. This session addresses topics in physical design flows, design planning, manufacturing, and automotive electronics. Following the successful discussions from last year, an invited session on Monday afternoon will continue the deep dive into analog design automation, with talks on the algorithmic, tool, and platform perspectives. An invited session on Tuesday morning will focus on timely research topics related to 3D ICs. Additionally, there are invited talks on chip- and package-level routing and on the impact of local interconnects in microprocessors. Since 2005, ISPD has become a crucial driving force for pushing research advancements in placement, global routing, and clock network synthesis, by holding highly competitive contests in these topics and by releasing large-scale real-world benchmark suites. This year's highperformance clock network synthesis contest continues this successful tradition and has attracted a large number of participants from all over the world. The results of this contest will be announced by the ISPD Contest Chair, along with the release of new benchmarks for clock synthesis.
ISBN	9781605589206
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-03-14
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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