NDLI: Physical design challenges beyond the 22nm node

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Going with the flow: bridging the gap between theory and practice in physical design

Thinking outside of the chip

Analog layout synthesis: what's missing?

Adding a new dimension to physical design

Logical and physical restructuring of fan-in trees

Dummy fill optimization for enhanced manufacturability

Skew management of NBTI impacted gated clock trees

Impact of local interconnects on timing and power in a high performance microprocessor

SafeChoice: a novel clustering algorithm for wirelength-driven placement

Physical design of biological systems

Design planning trends and challenges

B-escape: a simultaneous escape routing algorithm based on boundary routing

Design platform for electrical and physical co-design of analog circuits

Physical design implementation for 3D IC: methodology and tools

Ultra-fast interconnect driven cell cloning for minimizing critical path delay

Density gradient minimization with coupling-constrained dummy fill for CMP control

Accurate clock mesh sizing via sequential quadraticprogramming

Interconnect power and delay optimization by dynamic programming in gridded design rules

Droplet-routing-aware module placement for cross-referencing biochips

What makes a design difficult to route

FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction

Automatic generation of hierarchical placement rules for analog integrated circuits

Efficient design practices for thermal management of a TSV based 3D IC system

ITOP: integrating timing optimization within placement

Total sensitivity based dfm optimization of standard library cells

ISPD 2010 high performance clock network synthesis contest: benchmark suite and results

Performance study of VeSFET-based, high-density regular circuits

A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochips

Physical design challenges beyond the 22nm node

Completing high-quality global routes

An analytical placer for mixed-size 3D placement

Physical synthesis of bus matrix for high bandwidth low power on-chip communications

A matching based decomposer for double patterning lithography

A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems

Challenges and opportunities in optimization of automotive electronics

Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles

Physical design challenges beyond the 22nm node

Content Provider	ACM Digital Library
Author	Nassif, Sani R. Nowka, Kevin J.
Abstract	Producing working chips in current (32nm) and forthcoming CMOS technologies feels a lot like trying to create an intricate oil painting using a broom! After all, we are using light with a wavelength of 193nm to create shapes less than a tenth of a wavelength in dimension. But this pheneomena is well known to all who work in the area of VLSI, and much has been made of the tremendous gains our industry has made over the years. These innovations and gains will need to continue for a few more years, at least, until the replacement for Silicon is found. As we have continued technology scaling, the physical design rules that constrain what the layout of a circuit look like have changed. In earlier technologies, design rules were driven primarily by equipment and material limitations, as well as particulate contamination (defects). In today's technologies, the design rules have become much more complex because they are now being increasingly driven by lithographic constraints. One important new phenomena has been the increase in design rules that enforce various forms of regularity on the design. Restricted polysilicon orientation, width and pitch being one common example. From this perspective, one can imagine a scenario where increasing layout restrictions are applied in order to allow further scaling. Since different layers have different resolution requirements, with the top-most metal layers (so-called fat metal) having the least challenging lithography, such layout restrictions will likely be applied bottom up. Thus the bottom-most metal layers, which have the tightest design rules, get impacted by regularity first, followed by the intermediate layers, and so on. If we examine current layout practice at the 32nm node, we observe that the polysilicon layer is already quite regular. The hard lithography problems, however, have migrated to the first metal layer -commonly referred to as M1. The M1 layer typically has similar dimensions to the polysilicon layer, so it is understandable that it would present significant lithography challenges. Furthermore, creating dense layouts of complex circuit topologies like latches and multiplexors cannot be done without introducing a certain amount of topological complexity in within-cell routing. Herein lies the first challenge in moving to the 22nm node and beyond: balancing the desire for density with that of image fidelity. How can physical design help with this problem? It strikes the author that much attention is paid to numerous global aspects of physical chip design, i.e. placement, global routing, congestion management and so on. But in the end, the assumption is that the individual leaf cells are fixed, opaque (except for pin locations perhaps) and -- most disturbingly --uninteresting. While some of this information hiding is necessary to manage the complexity of the design process, one cannot help thinking of ways in which some effective cross-optimization might happen.
Starting Page	13
Ending Page	14
Page Count	2
File Format	PDF
ISBN	9781605589206
DOI	10.1145/1735023.1735029
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2010-03-14
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Technology Scaling
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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