NDLI: Mechanisms for bounding vulnerabilities of processor structures

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Mechanisms for bounding vulnerabilities of processor structures

Content Provider	ACM Digital Library
Author	Sivasubramaniam, Anand Parashar, Angshuman Soundararajan, Niranjan Kumar
Abstract	Concern for the increasing susceptibility of processor structures to transient errors has led to several recent research efforts that propose architectural techniques to enhance reliability. However, real systems are typically required to satisfy hard reliability budgets, and barring expensive full-redundancy approaches, none of the proposed solutions treat any reliability budgets or bounds as hard constraints. Meeting vulnerability bounds requires monitoring vulnerabilities of processor structures and taking appropriate actions whenever these bounds are violated. This mandates treating reliability as a first-order microarchitecture design constraint, while optimizing performance as long as reliability requirements are satisfied. This paper makes three key contributions towards this goal: (i) we present a simple infrastructure to monitor and provide upper bounds on the vulnerabilities of key processor structures at cycle-level fidelity; (ii) we propose two distinct control mechanisms - throttling and selective redundancy - to proactively and/or reactively bound the vulnerabilities to any limit specified by the system designer; (iii) within this framework, we propose a novel adaptation of Out-of-Order Commit for vulnerability reduction, which automatically provides additional leverage for the control mechanisms to boost performance while remaining within the reliability budget.
Starting Page	506
Ending Page	515
Page Count	10
File Format	PDF
ISBN	9781595937063
DOI	10.1145/1250662.1250725
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-06-09
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Microarchitecture Transient faults Redundant threading
Content Type	Text
Resource Type	Article

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