NDLI: Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance

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Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance

Content Provider	ACM Digital Library
Author	Parthasarathy, Sailashri Rotenberg, Eric Reddy, Vimal K.
Abstract	Redundant threading architectures duplicate all instructions to detect and possibly recover from transient faults. Several lighter weight Partial Redundant Threading (PRT) architectures have been proposed recently. (i) Opportunistic Fault Tolerance duplicates instructions only during periods of poor single-thread performance. (ii) ReStore does not explicitly duplicate instructions and instead exploits mispredictions among highly confident branch predictions as symptoms of faults. (iii) Slipstream creates a reduced alternate thread by replacing many instructions with highly confident predictions. We explore PRT as a possible direction for achieving the fault tolerance of full duplication with the performance of single-thread execution. Opportunistic and ReStore yield partial coverage since they are restricted to using only partial duplication or only confident predictions, respectively. Previous analysis of Slipstream fault tolerance was cursory and concluded that only duplicated instructions are covered. In this paper, we attempt to better understand Slipstream's fault tolerance, conjecturing that the mixture of partial duplication and confident predictions actually closely approximates the coverage of full duplication. A thorough dissection of prediction scenarios confirms that faults in nearly 100% of instructions are detectable. Fewer than 0.1% of faulty instructions are not detectable due to coincident faults and mispredictions. Next we show that the current recovery implementation fails to leverage excellent detection capability, since recovery sometimes initiates belatedly, after already retiring a detected faulty instruction. We propose and evaluate a suite of simple microarchitectural alterations to recovery and checking. Using the best alterations, Slipstream can recover from faults in 99% of instructions, compared to only 78% of instructions without alterations. Both results are much higher than predicted by past research, which claims coverage for only duplicated instructions, or 65% of instructions. On an 8-issue SMT processor, Slipstream performs within 1.3% of single-thread execution whereas full duplication slows performance by 14%.A key byproduct of this paper is a novel analysis framework in which every dynamic instruction is considered to be hypothetically faulty, thus not requiring explicit fault injection. Fault coverage is measured in terms of the fraction of candidate faulty instructions that are directly or indirectly detectable before.
Starting Page	83
Ending Page	94
Page Count	12
File Format	PDF
ISBN	1595934510
DOI	10.1145/1168857.1168869
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-10-23
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Time redundancy Value prediction Chip multiprocessor (cmp) Slipstream processor Transient faults Branch prediction Simultaneous multithreading (smt) Redundant multithreading
Content Type	Text
Resource Type	Article

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