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Mechanisms for Bounding Vulnerabilities of Processor Structures ABSTRACT
| Content Provider | CiteSeerX |
|---|---|
| Author | Soundararajan, Niranjan Parashar, Angshuman Sivasubramaniam, Anand |
| Abstract | Concern for the increasing susceptibility of processor structures to transient errors has led to several recent research efforts that propose architectural techniques to enhance reliability. However, real systems are typically required to satisfy hard reliability budgets, and barring expensive full-redundancy approaches, none of the proposed solutions treat any reliability budgets or bounds as hard constraints. Meeting vulnerability bounds requires monitoring vulnerabilities of processor structures and taking appropriate actions whenever these bounds are violated. This mandates treating reliability as a first-order microarchitecture design constraint, while optimizing performance as long as reliability requirements are satisfied. This paper makes three key contributions towards this goal: (i) we present a simple infrastructure to monitor and provide upper bounds on the vulnerabilities of key processor structures at cyclelevel fidelity; (ii) we propose two distinct control mechanisms – throttling and selective redundancy – to proactively and/or reactively bound the vulnerabilities to any limit specified by the system designer; (iii) within this framework, we propose a novel adaptation of Out-of-Order Commit for vulnerability reduction, which automatically provides additional leverage for the control mechanisms to boost performance while remaining within the reliability budget. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Processor Structure Abstract Bounding Vulnerability Processor Structure Reliability Budget Novel Adaptation Key Processor Structure Cyclelevel Fidelity Additional Leverage Several Recent Research Effort System Designer Appropriate Action Hard Reliability Budget Simple Infrastructure Distinct Control Mechanism Throttling Control Mechanism Transient Error Key Contribution Selective Redundancy First-order Microarchitecture Design Constraint Hard Constraint Vulnerability Reduction Expensive Full-redundancy Approach Reliability Requirement Out-of-order Commit Propose Architectural Technique Real System |
| Content Type | Text |
| Resource Type | Article |
