NDLI: FF-bond: multi-bit flip-flop bonding at placement

Content Provider	ACM Digital Library
Author	Luo, Guojie Tsai, Chang-Cheng Shi, Yiyu Jiang, Iris Hui-Ru
Abstract	Clock power contributes a significant portion of chip power in modern IC design. Applying multi-bit flip-flops can effectively reduce clock power. State-of-the-art work performs multi-bit flip-flop clustering at the post-placement stage. However, the solution quality may be limited because the combinational gates are immovable during the clustering process. To overcome the deficiency, in this paper, we propose multi-bit flip-flop bonding at placement. Inspired by ionic bonding in Chemistry, we direct flip-flops to merging friendly locations thus facilitating flip-flop merging. Experimental results show that our algorithm, called FF-Bond, can save 27% clock power on average. Compared with state-of-the-art post-placement multi-bit flip-flop clustering, FF-Bond can further reduce 14% clock power.
Starting Page	147
Ending Page	153
Page Count	7
File Format	PDF
ISBN	9781450319546
DOI	10.1145/2451916.2451955
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-03-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Multi-bit flip-flops Placement Clock power Timing
Content Type	Text
Resource Type	Article

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FF-bond: multi-bit flip-flop bonding at placement