NDLI: A compiler for scalable placement and routing of brain-like architectures

Please wait, while we are loading the content...

Heterogeneous 3-d stacking, can we have the best of both (technology) worlds?

Physical-aware system-level design for tiled hierarchical chip multiprocessors

Electromigration and its impact on physical design in future technologies

Dawn of computer-aided design: from graph-theory to place and route

Circuit and PD challenges at the 14nm technology node

Planning for local net congestion in global routing

A compiler for scalable placement and routing of brain-like architectures

ISPD 2013 expert designer/user session (eds)

Relative timing driven multi-synchronous design: enabling order-of-magnitude energy reduction

An improved benchmark suite for the ISPD-2013 discrete cell sizing contest

Opportunities and challenges for high performance microprocessor designs and design automation

To do or not to do hierarchical timing?

Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems

Data mining in design and test processes: basic principles and promises

Practicality on placement given by optimality of packing

Optical lithography extension with double patterning

Escape routing of mixed-pattern signals based on staggered-pin-array PCBs

Physical design for debug: insurance policy for IC's

Network flow based datapath bit slicing

TAU 2013 variation aware timing analysis contest

Variability aware hierarchical implementation of big chips

Benchmarking for research in power delivery networks of three-dimensional integrated circuits

SRAM dynamic stability verification by reachability analysis with consideration of threshold voltage variation

On the way to practical tools for beyond die codesign and integration

A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection

Delay-driven layer assignment in global routing under multi-tier interconnect structure

A top-down synthesis methodology for flow-based microfluidic biochips considering valve-switching minimization

FF-bond: multi-bit flip-flop bonding at placement

Challenges in managing timing and wiring contracts during hierarchical floorplanning and design closure

High performance and low power design techniques for ASIC and custom in nanometer technologies

PushPull: short path padding for timing error resilient circuits

Coding the objects in place and route CAD

Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling

SRP: simultaneous routing and placement for congestion refinement

Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure

Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes

Case study for placement solutions in ispd11 and dac12 routability-driven placement contests

Local merges for effective redundancy in clock networks

A compiler for scalable placement and routing of brain-like architectures

Content Provider	ACM Digital Library
Author	Srinivasa, Narayan
Abstract	The challenging aspect of building neuromorphic circuits in mature CMOS technology to match brain-like architectures is two-fold: scalability and connectivity. Scalability means that the circuits have to be expandable to match biological brains in terms of synaptic and neuronal densities. The challenge here is to implement 106 neurons and 1010 synapses with an average fanout of 104, in a square cm of CMOS [1, 2]. Connectivity means that the circuit has to offer the capability to have both short and long range (by physical distance) connections between neurons. A large part of this challenge is how to implement a connectivity of 104 synapses per neuron [3]. Unfortunately, even the exponential transistor density growth being experienced today is not sufficient to realize such massive connectivity and synaptic densities in a traditional CMOS process. Recent approaches to address these challenges have been to integrate CMOS with nanotechnology [4, 5] in order to achieve the required synaptic densities. These solutions use crossbar architectures predominantly but the connectivity challenge still remains a daunting task for such solutions [2, 6]. To meet these challenges, a novel synaptic time-multiplexing (STM) concept was developed along with a neural fabric design [7]. This combination has the advantage of offering greater flexibility and long range connectivity. It also provides a method to overcome the limitations of conventional CMOS technology to match the synaptic density and connectivity requirements found in mammalian brains while maintaining non-linear synapses and learning. In order to program neuromorphic hardware [8] for any desired brain architecture, the topology would first have to be converted into a connectivity matrix or a graph representation. This matrix along with the statistics on the number of neurons and synapses is provided as input to a neuromorphic compiler. The neuromorphic compiler compiles the neural network structure description into: 1) an assignment of the network's neurons and synapses to hardware neurons and virtual (multiplexed) synapses, and 2) a STM compatible routing schedule with switch states for the neural fabric at each STM timeslot. For each neuron, the exact location on the chip on the neural fabric should be determined. This is the placement problem. The quality of neuron placement can affect the ability of the routing algorithm to efficiently find the needed synaptic pathways to cover all the synapses within a STM duty cycle. For each synaptic pathway, a set of required grid lines from an output axon of the presynaptic neuron to an input dendrite of the postsynaptic neuron should be determined, and the switches on the way must be set to the ON state. This is the routing problem. The problem of routing and placement is closely related to problems in other programmable hardware such as the FPGA (Field Programmable Gate Array). There are some interesting differences between the neuromorphic solution proposed in this work and those designed for other programmable hardware such as the FPGA. In such applications, most current algorithms [9-11] for placing and routing expect a single timeslot and therefore do not have to address the immense routing demands placed by the problem described here. Unlike FPGA circuits, the neuromorphic hardware is expected to use every neuron device during routing. However, a study of FPGA architecture [12] show that on reconfigurable hardware 100% device utilization results in almost a 200% routing area increase due to congestion problems.
Starting Page	120
Ending Page	121
Page Count	2
File Format	PDF
ISBN	9781450319546
DOI	10.1145/2451916.2451946
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-03-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Compiler Brain-like architectures Placement Routing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing

SNet, a flexible, scalable network paradigm for manycore architectures

GART (abstract): a new, flexible placement and routing tool for research on FPGA architectures

Compiler support for selective page migration in NUMA architectures

Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures

SHARP: A Scalable Framework for Dynamic Joint Replica Placement and Request Routing Scheduling

A GRASP for Placement and Routing of Dataflow Process Networks on Many-Core Architectures

3D VLSI: A Scalable Integration Beyond 2D

A Reconfigurable Processor PARS and its Compiler

A compiler for scalable placement and routing of brain-like architectures

Similar Documents

Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing

SNet, a flexible, scalable network paradigm for manycore architectures

GART (abstract): a new, flexible placement and routing tool for research on FPGA architectures

Compiler support for selective page migration in NUMA architectures

Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures

SHARP: A Scalable Framework for Dynamic Joint Replica Placement and Request Routing Scheduling

A GRASP for Placement and Routing of Dataflow Process Networks on Many-Core Architectures

3D VLSI: A Scalable Integration Beyond 2D

A Reconfigurable Processor PARS and its Compiler

A compiler for scalable placement and routing of brain-like architectures