NDLI: A control-theoretic approach to dynamic voltage scheduling

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A control-theoretic approach to dynamic voltage scheduling

Content Provider	ACM Digital Library
Author	Sen, Mainak Choudhury, Suchismita Roy Varma, Ankush Ganesh, Brinda Jacob, Bruce Srinivasan, Lakshmi
Abstract	The development of energy-conscious embedded and/or mobile systems exposes a trade-off between energy consumption and system performance. Recent microprocessors have incorporated dynamic voltage scaling as a tool that system software can use to explore this trade-off. Developing appropriate heuristics to control this feature is a non-trivial venture; as has been shown in the past, voltage-scaling heuristics that closely track perceived performance requirements do not save much energy, while those that save the most energy tend to do so at the expense of performance resulting in poor response time, for example. We note that the task of dynamically scaling processor speed and voltage to meet changing performance requirements resembles a classical control-systems problem, and so we apply a bit of control theory to the task in order to define a new voltage-scaling algorithm. We find that, using our nqPID (not quite PID) algorithm, one can improve upon the current best-of-class heuristic Pering's AVGN algorithm, based on Govil's AGED AVERAGES algorithm and Weiser's PAST algorithm in both energy consumption and performance. The study is execution-based, not-trace-based; the voltage-scaling heuristics were integrated into an embedded operating system running on a Motorola M-CORE processor model. The applications studied are all members of the MediaBench benchmark suite.
Starting Page	255
Ending Page	266
Page Count	12
File Format	PDF
ISBN	1581136765
DOI	10.1145/951710.951744
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-10-30
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Nqpid Pid Dynamic voltage scaling Low-power
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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