NDLI: Automatic generation of application specific processors

Please wait, while we are loading the content...

Vectorizing for a SIMdD DSP architecture

Extending STI for demanding hard-real-time systems

Reducing code size with echo instructions

Frequent loop detection using efficient non-intrusive on-chip hardware

A new look at exploiting data parallelism in embedded systems

Encryption overhead in embedded systems and sensor network nodes: modeling and analysis

Graphical user interface energy characterization for handheld computers

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems

Moving from embedded systems to embedded computing

Simple offset assignment in presence of subword data

Clustered calculation of worst-case execution times

Compiler optimization and ordering effects on VLIW code compression

Increasing the number of effective registers in a low-power processor using a windowed register file

Fault-tolerant platforms for automotive safety-critical applications

AES and the cryptonite crypto processor

A hierarchical approach for energy efficient application design using heterogeneous embedded systems

Exploiting bank locality in multi-bank memories

Energy aware algorithm design via probabilistic computing: from algorithms and models to Moore's law and novel (semiconductor) devices

Efficient spill code for SDRAM

Task-level timing models for guaranteed performance in multiprocessor networks-on-chip

Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions

Automatic generation of application specific processors

Programming challenges in network processor deployment

A low-power accelerator for the SPHINX 3 speech recognition system

A control-theoretic approach to dynamic voltage scheduling

Lattice-based memory allocation

Cluster assignment of global values for clustered VLIW processors

System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures

A scalable wide-issue clustered VLIW with a reconfigurable interconnect

Architectural optimizations for low-power, real-time speech recognition

Power efficient encoding techniques for off-chip data buses

Performance, energy, and reliability tradeoffs in replicating hot cache lines

Polynomial-time algorithm for on-chip scratchpad memory partitioning

Automatic generation of application specific processors

Content Provider	ACM Digital Library
Author	Goodwin, David Petkov, Darin
Abstract	An application-specific instruction-set processor (ASIP) is ideally suited for embedded applications that have demanding performance, size, and power requirements that cannot be satisfied by a general purpose processor. ASIPs also have time-to-market and programmability advantages when compared to custom ASICs. The AutoTIE system simplifies the creation of ASIPs by automatically enhancing a base processor with application specific instruction set architecture (ISA) extensions, including instructions, operations, and register files. The new instructions, operations, and register files are automatically recognized and exploited by the entire software tool chain, including the C/C++ compiler. Thus, taking advantage of the generated ASIP does not require any changes to the application or any assembly language coding. AutoTIE uses the C/C++ compiler to analyze an application, and based on the analysis generates thousands, or even millions, of possible ISA extensions for the application. AutoTIE then uses performance and hardware estimation techniques to combine the ISA extensions into a large number of potential ASIPs, and for a range of hardware costs, chooses the ASIP that provides the maximum performance improvement. For example, for an application performing a radix-4 FFT, AutoTIE considers over 34,000 potential sets of ISA extensions. For hardware costs ranging from 7800 gates to 128,000 gates, AutoTIE combines these extensions to form 31 ASIPs, which provide performance improvements ranging from a factor of 1.12 to a factor of 11.3 compared to a general-purpose processor.
Starting Page	137
Ending Page	147
Page Count	11
File Format	PDF
ISBN	1581136765
DOI	10.1145/951710.951730
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-10-30
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Asips Extensible processors Configurable processors Automatic instruction-set generation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Automatic application-specific instruction-set extensions under microarchitectural constraints

Application specific instruction-set processors (asips) offer.

Scalable custom instructions identification for instruction-set extensible processors

Efficient instruction encoding for automatic instruction set design of configurable ASIPs (2002)

Code transformation strategies for extensible embedded processors

Modern Application Specific Instruction Set Processors (ASIPs) have

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors

Efficient custom instruction enumeration for extensible processors

Efficient instruction encoding for automatic instruction set design of configurable ASIPs

Automatic generation of application specific processors

Similar Documents

Automatic application-specific instruction-set extensions under microarchitectural constraints

Application specific instruction-set processors (asips) offer.

Scalable custom instructions identification for instruction-set extensible processors

Efficient instruction encoding for automatic instruction set design of configurable ASIPs (2002)

Code transformation strategies for extensible embedded processors

Modern Application Specific Instruction Set Processors (ASIPs) have

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors

Efficient custom instruction enumeration for extensible processors

Efficient instruction encoding for automatic instruction set design of configurable ASIPs

Automatic generation of application specific processors