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  1. Proceedings of the Fifth International Workshop on Network on Chip Architectures (NoCArc '12)
  2. Low power flitwise routing in an unidirectional torus with minimal buffering
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Network on metachip architectures
Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors
Junction based routing: a scalable technique to support source routing in large NoC platforms
Developing survival instincts in computing systems
Surface wave communication system for on-chip and off-chip interconnects
Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip
Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips
A structural analysis of evolved complex networks-on-chip
A high-efficiency low-cost heterogeneous 3D network-on-chip design
Variability-tolerant NoC link design
Low power flitwise routing in an unidirectional torus with minimal buffering

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Low power flitwise routing in an unidirectional torus with minimal buffering

Content Provider ACM Digital Library
Author Mische, Jörg Ungerer, Theo
Abstract State-of-the-art Network on Chips (NoCs) provide a high throughput and low latency by sending packets of data through a mesh topology, using virtual channels and wormhole flow control. The downside of this technology is a high area and energy consumption due to many buffers, large crossbars and a complex arbitration logic within the routers. In our approach, we avoid flow control and complex analysis of the head flit by sending single standalone flits instead of large packets of flits. As the order of flits is preserved between sending and receiving node, large data blocks can be sent anyway. The complexity of the router is further reduced by using an unidirectional 2D torus instead of a mesh, which reduces the number of router ports from 5 to 3. The flits are X-Y-routed and transported bufferless, as long as they stay within one dimension. Consequently there is only one FIFO per router, which buffers flits when they turn from X to Y direction. In terms of throughput and latency the so-called paternoster router is comparable with a conventional router with two virtual channels, but it consumes 50% less energy and 60% less area.
Starting Page 63
Ending Page 68
Page Count 6
File Format PDF
ISBN 9781450315401
DOI 10.1145/2401716.2401730
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2012-12-01
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Router microarchitecture Torus topology Network-on-chip
Content Type Text
Resource Type Article
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