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  1. Proceedings of the Fifth International Workshop on Network on Chip Architectures (NoCArc '12)
  2. A high-efficiency low-cost heterogeneous 3D network-on-chip design
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Network on metachip architectures
Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors
Junction based routing: a scalable technique to support source routing in large NoC platforms
Developing survival instincts in computing systems
Surface wave communication system for on-chip and off-chip interconnects
Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip
Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips
A structural analysis of evolved complex networks-on-chip
A high-efficiency low-cost heterogeneous 3D network-on-chip design
Variability-tolerant NoC link design
Low power flitwise routing in an unidirectional torus with minimal buffering

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A high-efficiency low-cost heterogeneous 3D network-on-chip design

Content Provider ACM Digital Library
Author Liljeberg, Pasi Tenhunen, Hannu Xu, Thomas Canhao Plosila, Juha
Abstract In this paper, we propose and analyze a heterogeneous Three Dimensional (3D) Network-on-Chip (NoC) design based on the optimized placement of vertical connections. NoC paradigm is expected to be the solution of future multicore processors, while 3D NoC extends the on-chip network vertically. Most previous research focus on symmetric, homogeneous, fully-connected 3D NoC designs. However, these designs may not be suitable for production and the market. The adoption of a 3D NoC design depends on the performance, power consumption and manufacturing cost of the chip. Here, we propose a 3D NoC design which improves performance, reduces power consumption and manufacturing cost. First, the vertical connections between layers are reduced and placed optimally. Second, the routers and links are redesigned to fit the heterogeneity nature of the network. The 3D NoC design is discussed with two configurations. We model a 64-core 3D NoC based on state-of-the-art 2D NoCs. A cycle accurate full system simulator is used for benchmark results. Experiments show that under different applications, the average execution times in two configurations are reduced by 5.5% and 20.7% respectively, compared with the homogeneous design. The average energy delay product of our design can achieve twice as better comparing with the diagonal heterogeneous design. This paper provides an inspiration for designing high performance, low power consumption and manufacturing cost 3D NoCs.
Starting Page 37
Ending Page 42
Page Count 6
File Format PDF
ISBN 9781450315401
DOI 10.1145/2401716.2401725
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2012-12-01
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Multicore Heterogeneous Network-on-chip 3d chip
Content Type Text
Resource Type Article
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