NDLI: Network on metachip architectures

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Network on metachip architectures

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Network on metachip architectures

Content Provider	ACM Digital Library
Author	Buckhanan, Wayne Hänninen, Ismo Niemier, Michael Bernstein, Gary H.
Abstract	The size of systems on a chip is limited by our ability to design and fabricate such systems, staying within the appropriate costs depending on the application. In this paper, we propose a divide-and-conquer approach, Quilt Packaging®, to be utilized for reducing the fabrication costs of large digital systems by partitioning them into a quilted "metachip" that offers integration density and performance merits surpassing the traditional system-on-chip. The physical partitioning and the network-on-a-quilt are closely linked, and should be designed concurrently. For this purpose, we present calculations on the silicon cost of the interconnects and partitioning, discuss the network granularity, and propose a multiprocessor design around a quilted modular network, offering novel techniques to improve the performance and enable true heterogeneous integration. Specifically, the silicon costs of the quilting method are demonstrated to be around 1% of the chip area, while the yield benefits can be in the tens of percents regime. The metachip concept enables the combination of standard high-density memory technologies and wide-bus access with improved performance, typically at least doubling the amount of memory vs. single-chip CMOS. Our modular quilted network enables the integration of non-CMOS chips into the quilt.
Starting Page	5
Ending Page	10
Page Count	6
File Format	PDF
ISBN	9781450315401
DOI	10.1145/2401716.2401719
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-12-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Quilt packaging Network-on-chip System-on-chip
Content Type	Text
Resource Type	Article

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