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  1. Proceedings of the Fifth International Workshop on Network on Chip Architectures (NoCArc '12)
  2. Variability-tolerant NoC link design
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Network on metachip architectures
Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors
Junction based routing: a scalable technique to support source routing in large NoC platforms
Developing survival instincts in computing systems
Surface wave communication system for on-chip and off-chip interconnects
Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip
Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips
A structural analysis of evolved complex networks-on-chip
A high-efficiency low-cost heterogeneous 3D network-on-chip design
Variability-tolerant NoC link design
Low power flitwise routing in an unidirectional torus with minimal buffering

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Variability-tolerant NoC link design

Content Provider ACM Digital Library
Author Abu-Elyazeed, M. F. El-Kharashi, M. Watheq Gawish, Eman Kamel
Abstract In this paper we propose a model for the design of Networks-on-Chip (NoC) links that takes into considerations the systematic and random effects of process variability. The model predicts the delay variations of each NoC link in a floor-plan. Delay variations are used to modify the link design parameters, like the optimal number of buffered sections and their gains, to meet the delay constraints in a more variability-tolerant way. The proposed technique is tested using test cases of 4x4 meshes at 65 nm, 45nm, 32nm, and 22 nm technologies. Results show that the delay variations approach 10% of the total link delay and the total power cost using our technique is up to 33% compared to the nominal delay and power values in the absence of random and systematic variations effects. Yet our methodology has a lower power cost compared to the worst-case design, saving up to 28% of the total power consumption in the test case of the 4x4 mesh at 45 nm.
Starting Page 57
Ending Page 62
Page Count 6
File Format PDF
ISBN 9781450315401
DOI 10.1145/2401716.2401729
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2012-12-01
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Buffered interconnect Process variability Floor-plan Link delay Networks-on-chip Link power consumptions
Content Type Text
Resource Type Article
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