NDLI: Networks-on-Chip topology generation techniques: Area and delay evaluation

Content Provider	IEEE Xplore Digital Library
Author	Morgan, A.A. Elmiligi, H. Watheq El-Kharashi, M. Gebali, F.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Victoria, Victoria, BC (Morgan, A.A.; Elmiligi, H.) \|\| Mentor Graphics Egypt, Cairo (Watheq El-Kharashi, M.; Gebali, F.)
Abstract	Networks-on-Chip (NoC) topology generation faces a trade-off between cost and performance. In this paper, we evaluate different custom and standard NoC topology generation techniques with respect to area and delay. The area needed for the topologies generated by these techniques is evaluated according to their routers area and number of global links. The delay is compared in terms of average internode distances. Our evaluation is done under both real and uniform traffic distributions. At the same time, we evaluate different network partitioning schemes. Kernighan-Lin (KL) partitioning is found to be the most suitable scheme for NoC topology generation. Results prove that custom topology generation techniques outperform standard techniques in terms of both area and delay. Network partitioning generation techniques result in topologies with lower area. Long-range insertion, which adds long-range links to standard mesh topology, is found to be the most delay-efficient technique.
Starting Page	33
Ending Page	38
File Size	114845
Page Count	6
File Format	PDF
ISBN	9781424434794
DOI	10.1109/IDT.2008.4802460
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-20
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Costs NoC topology generation techniques Telecommunication traffic Throughput Delay Fabrication Design engineering Network topology Network-on-a-chip networks-on-chip (NoC) Computer graphics network partitioning Long-range link insertion
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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