NDLI: A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures

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A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures

Content Provider	ACM Digital Library
Author	Lee, Hyung Gyu Baek, Seungcheol Nicopoulos, Chrysostomos Kim, Jongman
Abstract	Phase-Change Memory (PCM) is emerging as a promising new memory technology, due to its inherent ability to scale deeply into the nanoscale regime. However, PCM is still marred by a duet of potentially show-stopping deficiencies: poor write performance and limited durability. These weaknesses have urged designers to develop various supporting architectural techniques to aid and complement the operation of the PCM, while mitigating its innate flaws. One promising such solution is the deployment of hybridized memory architectures that fuse DRAM and PCM, in order to combine the best attributes of each technology. In this paper, we introduce a Dual-Phase Compression (DPC) scheme specifically optimized for DRAM/PCM hybrid environments. Extensive simulations with traces from real applications running on a full-system simulator of a multicore system demonstrate 35.1% performance improvement and 29.3% energy reduction, on average, as compared to a baseline DRAM/PCM hybrid implementation.
Starting Page	345
Ending Page	350
Page Count	6
File Format	PDF
ISBN	9781450312448
DOI	10.1145/2206781.2206865
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-05-03
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Dram/pcm hybrid architecture Pcm
Content Type	Text
Resource Type	Article

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