NDLI: STEP: a unified design methodology for secure test and IP core protection

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STEP: a unified design methodology for secure test and IP core protection

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STEP: a unified design methodology for secure test and IP core protection

Content Provider	ACM Digital Library
Author	Pradhan, Dhiraj K. Mathew, Jimson Shafik, Rishad A. Mohanty, Saraju P. Yeolekar, Pranav
Abstract	Intellectual property (IP) core based embedded systems design is a pervasive practice in the semiconductor industry due to shorter time-to-market and tougher cost competitions. Protecting the design information in these IP cores and securing test from various attacks are two emerging challenges in today's embedded systems design. Recently reported techniques address these challenges considering secure test and IP core protection separately. However, for ensuring high security during IP core functionality and also during test, joint consideration of secure test and IP core protection is much needed. In this paper, we propose a novel and unified design methodology, called STEP (Secure TEst and IP core Protection), which addresses the joint objective of secure test and IP core protection. The aim of STEP design methodology is to achieve high security at low system cost using the same key integrated hardware during test and IP core functionality. We evaluate the effectiveness of STEP design methodology considering advanced encryption standard (AES) system as a case study. We show that proposed design methodology benefits from high security and test accuracy, requiring up to 9% higher area and 20% power overheads.
Starting Page	333
Ending Page	338
Page Count	6
File Format	PDF
ISBN	9781450312448
DOI	10.1145/2206781.2206862
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-05-03
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Secure test Intellectual property core Security and protection
Content Type	Text
Resource Type	Article

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