NDLI: Parallel pipelined FFT architectures with reduced number of delays

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Parallel pipelined FFT architectures with reduced number of delays

Content Provider	ACM Digital Library
Author	Parhi, Keshab Ayinala, Manohar
Abstract	This paper presents a novel approach to design four and eight parallel pipelined fast Fourier transform (FFT) architectures using folding transformation. The approach is based on use of decimation in time algorithms which reduce the number of delay elements by 33% compared to the decimation in frequency based designs. The number of delay elements required for an N-point FFT architecture is N - 4 which is comparable to that of delay feedback schemes. The number of complex adders required is only 50% of those in the delay feedback designs. The proposed approach can be extended to any $radix-2^{n}$ based FFT algorithms. The proposed architectures are feed-forward designs and can be pipelined by more stages to increase the throughput. Further, a novel four parallel 128-point FFT architecture is derived using the proposed approach. It is shown that a $radix-2^{4}$ 4-parallel 128-point design requires 124 delay elements, 28 complex adders, and four full complex multipliers.
Starting Page	63
Ending Page	66
Page Count	4
File Format	PDF
ISBN	9781450312448
DOI	10.1145/2206781.2206798
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-05-03
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Four parallel Eight parallel Radix-2⁴ Fast fourier transform (fft) Decimation-in-time (dit) Folding
Content Type	Text
Resource Type	Article

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