NDLI: Proceedings of the great lakes symposium on VLSI (GLSVLSI '12)

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The role of photonics in future data centers

Ambipolar double-gate FETs for the design of compact logic structures

SNR analysis approach for hardware/software partitioning using dynamically adaptable fixed point representation

Breaking the power delivery wall using voltage stacking

Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit

Unifying functional and parametric timing verification

Distributed sensor data processing for many-cores

TSUNAMI: a light-weight on-chip structure for measuring timing uncertainty induced by noise during functional and test operations

Memristor: the illusive device

InMnAs magnetoresistive spin-diode logic

Stepwise sleep depth control for run-time leakage power saving

Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL

Extending symmetric variable-pair transitivities using state-space transformations

Towards systolic hardware acceleration for local complexity analysis of massive genomic data

Performance and energy models for memristor-based 1T1R RRAM cell

NBTI mitigation in microprocessor designs

An efficient CPI stack counter architecture for superscalar processors

Synchronization scheme for brick-based rotary oscillator arrays

New & improved models for SAT-based bi-decomposition

CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links

Lazy suspect-set computation: fault diagnosis for deep electrical bugs

An efficient approach for designing and minimizing reversible programmable logic arrays

An efficient power estimation methodology for complex RISC processor-based platforms

A denial-of-service resilient wireless NoC architecture

Crosslink insertion for variation-driven clock network construction

A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures

Accelerating thermal simulations of 3D ICs with liquid cooling using neural networks

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic

An optimized multicore cache coherence design for exploiting communication locality

A low-power all-digital GFSK demodulator with robust clock data recovery

Lithography-aware layout compaction

Voltage island-driven power optimization for application specific network-on-chip design

Influence of different layout styles on the performance of the calibration of an on-chip programmable voltage reference

Modeling a single electron turnstile in HSPICE

ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches

Sustainable multi-core architecture with on-chip wireless links

WRIP: logic restructuring techniques for wirelength-driven incremental placement

Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration

Efficient CMOL nanoscale hybrid circuit cell assignment using simulated evolution heuristic

Efficient selection and analysis of critical-reliability paths and gates

Parallel pipelined FFT architectures with reduced number of delays

Link breaking methodology: mitigating noise within power networks

A design approach dedicated to network-based and conflict-free parallel interleavers

Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs

Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates

Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits

A low stand-by power start-up circuit for SMPS PWM controller

SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells

STEP: a unified design methodology for secure test and IP core protection

Efficient folded VLSI architectures for linear prediction error filters

Design of an RNS reverse converter for a new five-moduli special set

A novel hybrid FIFO asynchronous clock domain crossing interfacing method

Synergistic integration of code encryption and compression in embedded systems

On the automatic synthesis of parallel SW from RTL models of hardware IPs

Density-reduction-oriented layer assignment for rectangle escape routing

Top-down-based symmetrical buffered clock routing

NBTI effects on tree-like clock distribution networks

Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis

A framework for high-level synthesis of heterogeneous MP-SoC

A fully integrated switched-capacitor DC-DC converter with dual output for low power application

Memory-based computing for performance and energy improvement in multicore architectures

High-level modeling of power consumption in active linear analog circuits

Share memory aware scheduler: balancing performance and fairness

A novel power-gating scheme utilizing data retentiveness on caches

Alleviating NBTI-induced failure in off-chip output drivers

A zero-overhead IC identification technique using clock sweeping and path delay analysis

Mitigating electromigration of power supply networks using bidirectional current stress

RAPA: reliability-aware priority arbitration strategy for network on chip

Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage

A high-performance online assay interpreter for digital microfluidic biochips

A scalable threshold logic synthesis method using ZBDDs

Reliable logic mapping on Nano-PLA architectures

A memristor-based TCAM (ternary content addressable memory) cell: design and evaluation

Proceedings of the great lakes symposium on VLSI (GLSVLSI '12)

Content Provider	ACM Digital Library
Editor	Stevens, Ken Cavallaro, Joseph R. Davis, Al Zhang, Tong Brunvard, Erik
Copyright Year	2012
Abstract	Welcome to the 22nd edition of the Great Lakes Symposium on VLSI (GLSVLSI) 2012 held in Salt Lake City, Utah at the Salt Lake Marriott, City Center. GLSVLSI is a premier venue for the dissemination of manuscripts of the highest quality in all areas related to VLSI, devices and systemlevel design. The venue of this year's GLSVLSI is Salt Lake City, which is located right next to the "Great Salt Lake." You will enjoy the beautiful Utah Mountains and surrounding scenery as well as the program over the two days of this year's GLSVLSI activity. As for the technical meeting, GLSVLSI 2012 was a resounding success: 144 papers were submitted, including authors from 34 different countries, of which 41 papers were accepted for oral presentation at the symposium (a 28% acceptance rate). With poster papers, a total of 71 papers will be presented at the symposium and published in the conference proceedings. The final technical program consists of 23 full presentations and 18 short presentations in 10 oral sessions and 30 posters in two poster sessions. GLSVLSI 2012 starts on Thursday, May 3rd, in the morning with an invited keynote talk followed by technical sessions on Emerging Technologies, Reliability, Circuit Design, CAD, Multi-core and NOC, Testing and Fault-Tolerance. Then, the technical program continues on Friday, May 4th with the second invited keynote talk followed by technical sessions which present the latest industrial and academic research covering topics such as Post-CMOS Circuits, Low Power, CAD, and VLSI Systems. The technical program of GLSVLSI 2012 includes two parallel tracks to allow longer presentations and discussions during the two days of the conference. Overall, there are ten regular sessions in the technical program with a poster session after lunch each day. We are also looking forward to the two plenary speeches that will be delivered by Al Davis, University of Utah on "The Role of Photonics in Future Data Centers", and by Khaled Salama, King Abdullah University of Science and Technology on "Memristor: The Illusive Device." Congratulations to Jia Zhao, Russell Tessier, and Wayne Burleson from University of Massachusetts, Amherst, for winning the GLSVLSI 2012 Best Student Paper Award for their paper, "Distributed Sensor Data Processing for Many-cores.".
ISBN	9781450312448
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-05-03
Access Restriction	Subscribed
Content Type	Text
Resource Type	Conference Proceedings

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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