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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chandrabose, K.K. Paramasivam, C. |
| Copyright Year | 2015 |
| Description | Author affiliation: Dept. of Electron. & Commun. Eng., K.S.Rangasamy Coll. of Technol., Namakkal, India (Chandrabose, K.K.; Paramasivam, C.) |
| Abstract | This paper presents a novel approach to develop pipelined architectures for fast Fourier transform (FFT) and Inverse fast Fourier transform (IFFT). For reducing area and time complexity, the architectures use hard wired Twiddle factor storage and new switching circuit for complex multiplication and that is employed in four point FFT/IFFT architectures. Pipelined Architectures for complex valued fast Fourier transform and Inverse fast Fourier transform are derived. This projected design is intended based on feed forward designs and may be extended to any radix $2^{n}$ based FFT/IFFT algorithm to extend the throughput. The projected FFT/IFFT design was synthesized by Synopsys design Compiler using the TSMC 90-nm library, and also the projected designs provide less latency and high Throughput than the reference FFT design. The design also synthesized for various Xilinx field-programmable gate-array platforms that also shows comparable results. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 2959895 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479968176 |
| e-ISBN | 9781479968183 |
| DOI | 10.1109/ICIIECS.2015.7193223 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-03-19 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | VLSI Very large scale integration Fast Fourier transform (FFT) Complexity theory Table lookup Inverse fast Fourier transform (IFFT) Tin Parallel processing Delays Pipelining Switching circuit Adders Radix-2 |
| Content Type | Text |
| Resource Type | Article |
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