NDLI: Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction

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Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction

Content Provider	ACM Digital Library
Author	Memik, Seda Ogrenci Ni, Min
Abstract	Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinational blocks to be used by slower blocks to meet a more stringent clock cycle time. Instead, we can leverage on the borrowed time to achieve leakage power reduction during gate sizing and/or dual $V_{th}$ assignment. In this paper, we present the first approach to the best of our knowledge for integrating clock skew scheduling, threshold voltage assignment, and gate sizing into one optimization formulation. Over 29 circuits in the ISCAS89 benchmark suite, this integrated approach can reduce leakage power by as much as 55.83% and by 18.79% on average, compared to using combinational circuit based power optimization on each combinational block without considering clock skews. Using a 65nm dual $V_{th}$ technology library, this corresponds to a 23.87% peak reduction (6.15% on average) in total power at the ambient operating temperature. The average total power reduction further increases to 9.83% if the high temperature library of the same process technology is used.
Starting Page	610
Ending Page	613
Page Count	4
File Format	PDF
ISBN	9781605581156
ISSN	0738100X
DOI	10.1145/1391469.1391625
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-06-08
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Clock skew scheduling Leakage power optimization Gate sizing Dual-vth
Content Type	Text
Resource Type	Article

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