NDLI: Automatic synthesis of clock gating logic with controlled netlist perturbation

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Flow engineering for physical implementation: theory and practice

Sparse matrix computations on manycore GPU's

Functionally linear decomposition and synthesis of logic circuits for FPGAs

Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations

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High-performance timing simulation of embedded software

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Next generation wireless-multimedia devices: who is up for the challenge?

Statistical diagnosis of unmodeled systematic timing effects

Automatic architecture refinement techniques for customizing processing elements

Parameterized timing analysis with general delay models and arbitrary variation sources

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SystemClick: a domain-specific framework for early exploration using functional performance models

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An efficient incremental algorithm for min-area retiming

Verifying really complex systems: on earth and beyond

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

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Standard interfaces in mobile terminals: increasing the efficiency of device design and accelerating innovation

Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verification

Variation-adaptive feedback control for networks-on-chip with multiple clock domains

Keeping hot chips cool: are IC thermal problems hot air?

Bi-decomposing large Boolean functions via interpolation and satisfiability solving

3-D semiconductor's: more from Moore

Efficient Monte Carlo based incremental statistical timing analysis

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Stochastic modeling of a thermally-managed multi-core system

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Strategies for mainstream usage of formal verification

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Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness

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Partial order reduction for scalable testing of systemC TLM designs

Automated hardware-independent scenario identification

Modeling crosstalk in statistical static timing analysis

Custom is from Venus and synthesis from Mars

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FPGA area reduction by multi-output function based sequential resynthesis

Topology synthesis of analog circuits based on adaptively generated building blocks

Rapid application specific floating-point unit generation with bit-alignment

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DeFer: deferred decision making enabled fixed-outline floorplanner

Feedback-controlled reliability-aware power management for real-time embedded systems

Automated design of self-adjusting pipelines

Translation of an existing VMM-based SystemVerilog testbench to OVM

The mixed signal optimum energy point: voltage and parallelism

Functional test selection based on unsupervised support vector analysis

Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement

Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts

Cache modeling in probabilistic execution time analysis

Programmable logic circuits based on ambipolar CNFET

Multiple defect diagnosis using no assumptions on failing pattern characteristics

Formal datapath representation and manipulation for implementing DSP transforms

DeMOR: decentralized model order reduction of linear networks with massive ports

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Transistor level gate modeling for accurate and fast timing, noise, and power analysis

Applying passive RFID system to wireless headphones for extreme low power consumption

Predictive formulae for OPC with applications to lithography-friendly routing

Scalable min-register retiming under timing and initializability constraints

Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM

SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models

Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration

Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements

Application mapping for chip multiprocessors

Signature based Boolean matching in the presence of don't cares

Tera-scale computing and interconnect challenges

Generalized Krylov recycling methods for solution of multiple related linear equation systems in electromagnetic analysis

Circuit-wise buffer insertion and gate sizing algorithm with scalability

Predictive dynamic thermal management for multicore systems

ADAM: run-time agent-based distributed application mapping for on-chip communication

Reconfigurable computing using content addressable memory for improved performance and resource usage

Pre-RTL formal verification: an intel experience

Scan chain clustering for test power reduction

Design of high performance pattern matching engine through compact deterministic finite automata

A power and temperature aware DRAM architecture

Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters

On the role of timing masking in reliable logic circuit design

Construction of concrete verification models from C++

Predictive design space exploration using genetically programmed response surfaces

Power gating scheduling for power/ground noise reduction

Parallelizing CAD: a timely research agenda for EDA

A generalized network flow based algorithm for power-aware FPGA memory mapping

Analog placement based on hierarchical module clustering

Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency

iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor

Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation

Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs

Energy-optimal software partitioning in heterogeneous multiprocessor embedded systems

Speedpath prediction based on learning from a small set of examples

Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs

Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic

A progressive-ILP based routing algorithm for cross-referencing biochips

Exploring locking & partitioning for predictable shared caches on multi-cores

Multiprocessor performance estimation using hybrid simulation

Analog parallelism in ring-based VCOs

Precise failure localization using automated layout analysis of diagnosis candidates

Symbolic noise analysis approach to computational hardware optimization

Stochastic integral equation solver for efficient variation-aware interconnect extraction

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

A "true" electrical cell model for timing, noise, and power grid verification

Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems

Dose map and placement co-optimization for timing yield enhancement and leakage power reduction

Merging nodes under sequential observability

Topological routing to maximize routability for package substrate

Specify-explore-refine (SER): from specification to implementation

Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability

Concurrent topology and routing optimization in automotive network integration

The synthesis of robust polynomial arithmetic with stochastic logic

Design and CAD for 3D integrated circuits

A framework for block-based timing sensitivity analysis

Type-matching clock tree for zero skew clock gating

Control theory-based DVS for interactive 3D games

Latency and bandwidth efficient communication through system customization for embedded multiprocessors

Automated transistor sizing for FPGA architecture exploration

Challenges in using system-level models for RTL verification

On reliable modular testing with vulnerable test access mechanisms

SHIELD: a software hardware design methodology for security and reliability of MPSoCs

Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling

Leakage power reduction using stress-enhanced layouts

Study of the effects of MBUs on the reliability of a 150 nm SRAM device

Predictive runtime verification of multi-processor SoCs in SystemC

Efficient system design space exploration using machine learning techniques

Forbidden transition free crosstalk avoidance CODEC design

Enhancing timing-driven FPGA placement for pipelined netlists

C-based design flow: a case study on G.729A for voice over internet protocol (VoIP)

Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor

Faster symmetry discovery using sparsity of symmetries

Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips

Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques

Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays

Miss reduction in embedded processors through dynamic, power-friendly cache design

Multithreaded simulation for synchronous dataflow graphs

Techniques for fully integrated intra-/inter-chip optical communication

IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors

Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform

Electric field integral equation combined with cylindrical conduction mode basis functions for electrical modeling of three-dimensional interconnects

A practical approach of memory access parallelization to exploit multiple off-chip DDR memories

Challenges in gate level modeling for delay and SI at 65nm and below

Automated design of tunable impedance matching networks for reconfigurable wireless applications

Design-process integration for performance-based OPC framework

N-variant IC design: methodology and applications

Low power passive equalizer optimization using tritonic step response

Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers

Automatic synthesis of clock gating logic with controlled netlist perturbation

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Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications

Robust chip-level clock tree synthesis for SOC designs

Many-core design from a thermal perspective

Federation: repurposing scalar cores for out-of-order instruction issue

TuneFPGA: post-silicon tuning of dual-Vdd FPGAs

Leveraging sequential equivalence checking to enable system-level to RTL flows

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A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer

Temperature management in multiprocessor SoCs using online learning

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An automatic scratch pad memory management tool and MPEG-4 encoder case study

Statistical waveform and current source based standard cell models for accurate timing analysis

How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach

Driver waveform computation for timing analysis with multiple voltage threshold driver models

Addressing library creation challenges from recent Liberty extensions

A new paradigm for synthesis and propagation of clock gating conditions

Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution

Path smoothing via discrete optimization

Compiler-driven register re-assignment for register file power-density and temperature reduction

ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor

An embedded infrastructure of debug and trace interface for the DSP platform

DVFS in loop accelerators using BLADES

Process variation tolerant SRAM array for ultra low voltage applications

Bounded-lifetime integrated circuits

PicoCube: a 1 $cm^{3}$ sensor node powered by harvested energy

Collective computing based on swarm intelligence

An 8x8 run-time reconfigurable FPGA embedded in a SoC

(Bio)-behavioral CAD

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