NDLI: How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach

Content Provider	ACM Digital Library
Author	Bougard, Bruno Li, Min Catthoor, Francky Van Der Perre, Liesbet Novo, David
Abstract	Nowadays, mobile devices are integrating an increasing variety of wireless communication standards, and each standard demands a multitude of modes. This tremendous diversity, combined with the increasing development-cost of deep-submicron silicon, desires highly flexible baseband implementations. The tier-2 SDR (Software Defined Radio) paradigm, where the entire baseband runs on programmable architectures, is very attractive to obtain the desired flexibility. Parallel ISP (Instruction Set Processor) based SDR baseband platforms have attracted extensive interest in recent years. However, such implementations typically come with a much lower energy-efficiency than traditional implementations as ASICs (Application Specific Integrated Circuits). This energy efficiency gap remains to be bridged in order to make SDR more pervasive. Importantly, the gap is becoming even more and more challenging in emerging high rate communication standards, such as 3GPP LTE, Mobile WiMAX and 802.11n. This situation demands disruptive innovations.
Starting Page	345
Ending Page	346
Page Count	2
File Format	PDF
ISBN	9781605581156
ISSN	0738100X
DOI	10.1145/1391469.1391559
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-06-08
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Sdr Wireless Baseband Low power
Content Type	Text
Resource Type	Article

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How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach