NDLI: A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits

Please wait, while we are loading the content...

EDA: this is serious business

Design optimizations for microprocessors at low temperature

Reducing clock skew variability via cross links

Industrial experience with test generation languages for processor verification

Modular scheduling of guarded atomic actions

Design and reliability challenges in nanometer technologies

When IC yield missed the target, who is at fault?

Memory access scheduling and binding considering energy minimization in multi-bank memory systems

Abstraction of assembler programs for symbolic worst case execution time analysis

Automated design of operational transconductance amplifiers using reversed geometric programming

Buffer sizing for clock power minimization subject to general skew constraints

What happened to ASIC?: Go (recon)figure?

Optical proximity correction (OPC): friendly maze routing

An efficient finite-domain constraint solver for circuits

An integrated hardware/software approach for run-time scratchpad management

Competitive strategies for the electronics industry

Business models in IP, software licensing, and services

Timing closure for low-FO4 microprocessor design

Verification: what works and what doesn't

Leakage aware dynamic voltage scaling for real-time embedded systems

Communication-efficient hardware acceleration for fast functional simulation

Toward a methodology for manufacturability-driven design rule exploration

First-order incremental block-based statistical timing analysis

System level design: six success stories in search of an industry

Large-scale placement by grid-warping

Passivity-preserving model reduction via a computationally efficient project-and-balance scheme

Automatic translation of software binaries onto FPGAs

Platform based design: does it answer the entire SoC challenge?

A recursive paradigm to solve Boolean relations

Parametric yield estimation considering leakage variability

System design for DSP applications in transaction level modeling paradigm

On path-based learning and its applications in delay test and diagnosis

Is statistical timing statistically significant?

AMUSE: a minimally-unsatisfiable subformula extractor

Were the good old days all that good?: EDA then and now

Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding

A method for correcting the functionality of a wire-pipelined circuit

Defect tolerant probabilistic design paradigm for nanotechnologies

Design tools for BioMEMS

Will Moore's Law rule in the land of analog?

Profile-guided microarchitectural floorplanning for deep submicron processor design

Worst-case circuit delay taking into account power supply variations

Design and implementation of the POWER5™ microprocessor

The future of multiprocessor systems-on-chips

Modeling repeaters explicitly within analytical placement

A novel approach for flexible and consistent ADL-driven ASIP design

FPGA power reduction using configurable dual-Vdd

Security as a new dimension in embedded system design

Tradeoffs between date oxide leakage and delay for dual $T_{ox}$ circuits

Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics

Re-synthesis for delay variation tolerance

A frequency relaxation approach for analog/RF system-level simulation

Theoretical and practical limits of dynamic voltage scaling

Noise characterization of static CMOS gates

Debugging HW/SW interface for MPSoC: video encoder system design case study

On the generation of scan-based test sets with reachable states for testing under functional operation conditions

Virtual memory window for application-specific reconfigurable coprocessors

Introduction to special issue: Novel paradigms in system-level design

Platform-based network design (with emphasis on wireless networks)

Is Statistical Timing Statistically Significant?

Leakage in nano-scale technologies: mechanisms, impact and design considerations

Fast and flexible buffer trees that navigate the physical layout environment

Defining coverage views to improve functional coverage analysis

Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis

A communication-theoretic design paradigm for reliable SOCs

Profile-based optimal intra-task voltage scheduling for hard real-time applications

Extending the transaction level modeling approach for fast communication architecture exploration

Correct-by-construction layout-centric retargeting of large analog designs

Optimal placement of power supply pads and pins

Design automation for mask programmable fabrics

Automatic abstraction and verification of verilog models

Multi-profile based code compression

Forest vs. trees: where's the slack?

Retargetable profiling for rapid, early system-level design space exploration

A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication

Phase correct routing for alternating phase shift masks

Fast statistical timing analysis handling arbitrary delay correlations

Placement feedback: a concept and method for better min-cut placements

A linear fractional transform (LFT) based model for interconnect parametric uncertainty

Area-efficient instruction set synthesis for reconfigurable system-on-chip designs

Nomadic platform approach for wireless mobile multimedia

A robust algorithm for approximate compatible observability don't care (CODC) computation

A methodology to improve timing yield in the presence of process variations

An analytical approach for dynamic range estimation

Efficient on-line testing of FPGAs with provable diagnosabilities

A SAT-based algorithm for reparameterization in symbolic simulation

Energy-aware deterministic fault tolerance in distributed real-time embedded systems

A new approach to latency insensitive design

Architecture-level synthesis for automatic interconnect pipelining

CAD challenges in BioMEMS design

Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects

Statistical gate delay model considering multiple input switching

A dual-core 64b ultraSPARC microprocessor for dense server applications

Heterogeneous MP-SoC: the solution to energy-efficient signal processing

Quadratic placement using an improved timing model

Characterizing embedded applications for instruction-set extensible processors

Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources

Implicit pseudo boolean enumeration algorithms for input vector control

A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS

Post-layout logic optimization of domino circuits

Robust, stable time-domain methods for solving MPDEs of fast/slow systems

Enabling energy efficiency in via-patterned gate array devices

A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits

SUNMAP: a tool for automatic topology selection and generation for NoCs

Scalable selector architecture for x-tolerant deterministic BIST

Dynamic FPGA routing for just-in-time FPGA compilation

System level design paradigms: Platform-based design and communication synthesis

Communication-centric SOC design

System level leakage reduction considering the interdependence of temperature and leakage

Practical repeater insertion for low power: what repeater library do we need?

Systematic functional coverage metric synthesis from hierarchical temporal event relation graph

A timing-driven module-based chip design flow

Reliable communication in systems on chips

Requirement-based design methods for adaptive communications links

Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware

Fast and accurate parasitic capacitance models for layout-aware

A stochastic approach To power grid analysis

On designing via-configurable cell blocks for regular fabrics

Abstraction refinement by controllability and cooperativeness analysis

An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory

Efficient timing closure without timing driven placement and routing

High level cache simulation for heterogeneous multiprocessors

Circuit-aware architectural simulation

Toward a systematic-variation aware timing methodology

STAC: statistical timing analysis with correlation

Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions

Variational delay metrics for interconnect timing analysis

Data compression for improving SPM behavior

Benefits and challenges for platform-based design

A method to decompose multiple-output logic functions

Novel sizing algorithm for yield improvement under process variation in nanometer technology

Automated fixed-point data-type optimization tool for signal processing and communication systems

On test generation for transition faults with minimized peak power dissipation

Exploiting structure in symmetry detection for CNF

Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices

Pre-layout wire length and congestion estimation

Automatic generation of equivalent architecture model from functional specification

A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representation

Static timing analysis using backward signal propagation

Low voltage swing logic circuits for a Pentium® 4 processor integer core

Flexible architectures for engineering successful SOCs

An approach to placement-coupled logic replication

Introduction of local memory elements in instruction set extensions

An SoC design methodology using FPGAs and embedded microprocessors

Statistical optimization of leakage power considering process variations using dual-Vth and sizing

CHIME: coupled hierarchical inductance model evaluation

Multiple constant multiplication by time-multiplexed mapping of addition chains

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects

Compact thermal modeling for temperature-aware design

A novel technique to improve noise immunity of CMOS dynamic logic circuits

FITS: framework-based instruction-set tuning synthesis for embedded application specific processors

Scan-BIST based on transition probabilities

An efficient algorithm for finding empty space for online FPGA placement

Computation and communication refinement for multiprocessor SoC design: A system-level perspective

Analysis and optimization of communication-dominated real-time embedded systems

Probabilistic regression suites for functional verification

Timing closure through a globally synchronous, timing partitioned design methodology

Designing robust microarchitectures

Automated energy/performance macromodeling of embedded software

LODS: locality-oriented dynamic scheduling for on-chip multiprocessors

ORACLE: optimization with recourse of analog circuits including layout extraction

Efficient power/ground network analysis for power integrity-driven design methodology

Routing architecture exploration for regular fabrics

Verifying a gigabit ethernet switch using SMV

Operating-system controlled network on chip

Selective gate-length biasing for cost-effective runtime leakage control

Exploiting input information in a model reduction algorithm for massively coupled parasitic networks

Trends in the use of re-configurable platforms

Symmetry detection for incompletely specified functions

Statistical timing analysis based on a timing yield model

An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design

A new state assignment technique for testing and low power

Refining the SAT decision ordering for bounded model checking

Adaptive data partitioning for ambient multimedia

The best of both worlds: the efficient asynchronous implementation of synchronous specifications

Divide-and-concatenate: an architecture level optimization technique for universal hash functions

Leakage-and crosstalk-aware bus encoding for total power reduction

Large-scale full-wave simulation

Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis

Hierarchical approach to exact symbolic analysis of large analog circuits

Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era

Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining

Mapping a domain specific language to a platform FPGA

Combining dictionary coding and LFSR reseeding for test data compression

Analysis and optimization of distributed real-time embedded systems

Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs

Hierarchical application aware error detection and recovery

Coding for system-on-chip networks: a unified framework

An area estimation methodology for FPGA based designs at systemc-level

A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits

Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs

Accurate pre-layout estimation of standard cell characteristics

A general decomposition strategy for verifying register renaming

DyAD: smart routing for networks-on-chip

Implicit enumeration of structural changes in circuit optimization

Synthesizing interconnect-efficient low density parity check codes

Automatic generation of breakpoint hardware for silicon debug

Efficient equivalence checking with partitions and hierarchical cut-points

Energy characterization of filesystems for diskless embedded systems

Fast hazard detection in combinational circuits

Performance analysis of different arbitration algorithms of the AMBA AHB bus

Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment

Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects

A new heuristic algorithm for reversible logic synthesis

An Essentially Non-Oscillatory (ENO) high-order accurate Adaptive table model for device modeling

Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs

Quantum logic synthesis by symbolic reachability analysis

Warp Processors

Module placement for fault-tolerant microfluidics-based biochips

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing

Simultaneous placement with clustering and duplication

A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks

A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits

Content Provider	ACM Digital Library
Author	Dey, Sujit Zhao, Chong Bai, Xiaoliang
Abstract	Circuits using nano-meter technologies are becoming increasingly vulnerable to signal interference from multiple noise sources as well as radiation-induced soft errors. One way to ensure reliable functioning of chips is to be able to analyze and identify the spots in the circuit which are susceptible to such effects (called "soft spots" in this paper), and to make sure such soft spots are "hardened" so as to resist multiple noise effects and soft errors. In this paper, we present a scalable soft spot analysis methodology to study the vulnerability of digital ICs exposed to nano-meter noise and transient soft errors. First, we define "softness" as an important characteristic to gauge system vulnerability. Then several key factors affecting softness are examined. Finally an efficient Automatic Soft Spot Analyzer (ASSA) is developed to obtain the softness distribution which reflects the unbalanced noise-tolerant capability of different regions in a design. The proposed methodology provides guidelines to reduction of severe nano-meter noise effects caused by aggressive design in the pre-manufacturing phase, and guidelines to selective insertion of on-line protection schemes to achieve higher robustness. The quality of the proposed soft-spot analysis technique is validated by HSPICE simulation, and its scalability is demonstrated on a commercial embedded processor.
Starting Page	894
Ending Page	899
Page Count	6
File Format	PDF
ISBN	1581138288
DOI	10.1145/996566.996804
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2004-06-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Softness distribution Nano-meter technology Robustness Compound noise effect
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in