NDLI: Area-efficient instruction set synthesis for reconfigurable system-on-chip designs

Content Provider	ACM Digital Library
Author	Sarrafzadeh, Majid Brisk, Philip Kaplan, Adam
Abstract	Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these compilers produce hardware that is larger than necessary, as they do not allow instructions to share hardware resources. This study presents an efficient heuristic which transforms a set of custom instructions into a single hardware datapath on which they can execute. Our approach is based on the classic problems of finding the longest common subsequence and substring of two (or more) sequences. This heuristic produces circuits which are as much as 85.33% smaller than those synthesized by integer linear programming (ILP) approaches which do not explore resource sharing. On average, we obtained 55.41% area reduction for pipelined datapaths, and 66.92% area reduction for VLIW datapaths. Our solution is simple and effective, and can easily be integrated into an existing silicon compiler.
Starting Page	395
Ending Page	400
Page Count	6
File Format	PDF
ISBN	1581138288
DOI	10.1145/996566.996679
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2004-06-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Compiler Field-programmable gate array (fpga) Integer linear programming (ilp) Resource sharing
Content Type	Text
Resource Type	Article

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Area-efficient instruction set synthesis for reconfigurable system-on-chip designs