NDLI: Leakage aware dynamic voltage scaling for real-time embedded systems

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Leakage aware dynamic voltage scaling for real-time embedded systems

Content Provider	ACM Digital Library
Author	Jejurikar, Ravindra Pereira, Cristiano Gupta, Rajesh
Abstract	A five-fold increase in leakage current is predicted with each technology generation. While Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also causes increased leakage energy drain by lengthening the interval over which a computation is carried out. Therefore, for minimization of the total energy, one needs to determine an operating point, called the critical speed. We compute processor slowdown factors based on the critical speed for energy minimization. Procrastination scheduling attempts to maximize the duration of idle intervals by keeping the processor in a sleep/shutdown state even if there are pending tasks, within the constraints imposed by performance requirements. Our simulation experiments show that the critical speed slowdown results in up to 5% energy gains over a leakage oblivious dynamic voltage scaling. Procrastination scheduling scheme extends the sleep intervals to up to 5 times, resulting in up to an additional 18% energy gains, while meeting all timing requirements.
Starting Page	275
Ending Page	280
Page Count	6
File Format	PDF
ISBN	1581138288
DOI	10.1145/996566.996650
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2004-06-07
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Procrastication Critical speed Real-time systems Edf scheduling Leakage power Low power scheduling
Content Type	Text
Resource Type	Article

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