NDLI: CONAN - a design exploration framework for reliable nano-electronics architectures

Content Provider	IEEE Xplore Digital Library
Author	Cotofana, S. Schmid, A. Leblebici, Y. Ionescu, A. Soffke, O. Zipf, P. Glesner, M. Rubio, A.
Copyright Year	2005
Description	Author affiliation: Delft Univ. of Technol., Netherlands (Cotofana, S.)
Abstract	In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our approach is a generic (parametrical) architectural template. Configurable nanostructures for reliable nano electronics (CONAN), which embeds support for reliability at various levels of abstractions. Some of the main reliability sources are regular and decentralized structures based on simple basic computation cells designed to be robust against disturbances and noise, fault tolerance based on hardware, time and information redundancy applied at the basic cell level as well as at higher levels, self diagnosis assisted by the dynamic reconfiguration of basic computation cells and interconnect rerouting. Within the CONAN template, both technology dependent and independent models co-exists such that the more abstract layers are technology independent while the lower levels can be retargeted to various fabrication technologies. Our proposal is application-oriented and allows the designers to deal with unpredictability, and low reliability, which are unavoidable characteristics of future emerging nano-devices. When combined with the underlying software, the tools supporting the CONAN approach allow the designer to check whether the design constraints are fulfilled before performing a detailed implementation and provides means to trade area, delay, and power consumptions for reliability. As such, this proposal is a call-to-arms to mobilize the efforts of systems designers in order to achieve a systematic design methodology for reliable systems.
Sponsorship	IEEE Comput. Soc. Tech. Comm. on VLSI
Starting Page	260
Ending Page	267
File Size	273902
Page Count	8
File Format	PDF
ISBN	0769524079
ISSN	21600511
DOI	10.1109/ASAP.2005.26
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-07-23
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design methodology Proposals Power system reliability Circuits Nanostructures Noise robustness Noise level Fault tolerance Hardware Redundancy
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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